R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 171

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

5.6
5.6.1
Exception handling can be triggered by trap instructions, slot illegal instructions, general illegal
instructions, integer division exceptions, and FPU exceptions, as shown in table 5.10.
Table 5.10 Types of Exceptions Triggered by Instructions
Type
Trap instruction
Slot illegal
instructions
General illegal
instructions
Integer division
exceptions
FPU exceptions
Exceptions Triggered by Instructions
Types of Exceptions Triggered by Instructions
Source Instruction
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot)
(including FPU instructions and
FPU-related CPU instructions in
FPU module standby state),
instructions that rewrite the PC,
32-bit instructions, RESBANK
instruction, DIVS instruction, and
DIVU instruction
Undefined code anywhere
besides in a delay slot (including
FPU instructions and FPU-related
CPU instructions in FPU module
standby statute)
Division by zero
Negative maximum value ÷ (−1)
Starts when detecting invalid
operation exception defined by
IEEE754, division-by-zero
exception, overflow, underflow, or
inexact exception.
Comment
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N
32-bit instructions: BAND.B, BANDNOT.B,
BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B,
MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S,
MOVU.B, MOVU.W.
DIVU, DIVS
DIVS
FADD, FSUB, FMUL, FDIV, FMAC,
FCMP/EQ, FCMP/GT, FLOAT, FTRC,
FCNVDS, FCNVSD, FSQRT
Rev. 3.00 Sep. 28, 2009 Page 139 of 1650
Section 5 Exception Handling
REJ09B0313-0300