R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 464

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 10 Direct Memory Access Controller (DMAC)
(1)
(a)
In dual address mode, both the transfer source and destination are accessed (selected) by an
address. The transfer source and destination can be located externally or internally.
DMA transfer requires two bus cycles because data is read from the transfer source in a data read
cycle and written to the transfer destination in a data write cycle. At this time, transfer data is
temporarily stored in the DMAC. In the transfer between external memories as shown in figure
10.5, data is read to the DMAC from one external memory in a data read cycle, and then that data
is written to the other external memory in a data write cycle.
Auto request, external request, and on-chip peripheral module request are available for the transfer
request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit in the
channel control register (CHCR) can specify whether the DACK is output in read cycle or write
cycle.
Rev. 3.00 Sep. 28, 2009 Page 432 of 1650
REJ09B0313-0300
Address Modes
Dual Address Mode
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Data buffer
Data buffer
Figure 10.5 Data Flow of Dual Address Mode
DMAC
DMAC
SAR
DAR
SAR
DAR
Second bus cycle
First bus cycle
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
module
module
module
module