R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 447

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Bit
9, 8
7 to 3
2
1
Bit Name
PR[1:0]
⎯
AE
NMIF
Initial
Value
00
All 0
0
0
R/W
R/W
R
R/(W)*
R/(W)*
1
1
Description
Priority Mode
These bits select the priority level between channels
when there are transfer requests for multiple channels
simultaneously.
00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 >
01: Fixed mode 2: CH0 > CH4 > CH1 > CH5 > CH2 >
10: Setting prohibited
11: Round-robin mode (only supported in CH0 to CH3)
Reserved
These bits are always read as 0. The write value
should always be 0.
Address Error Flag
Indicates whether an address error has occurred by
the DMAC. When this bit is set, even if the DE bit in
CHCR and the DME bit in DMAOR are set to 1, DMA
transfer is not enabled. This bit can only be cleared by
writing 0 after reading 1.*
0: No DMAC address error
1: DMAC address error occurred
[Clearing condition]
•
NMI Flag
Indicates that an NMI interrupt occurred. When this bit
is set, even if the DE bit in CHCR and the DME bit in
DMAOR are set to 1, DMA transfer is not enabled. This
bit can only be cleared by writing 0 after reading 1.*
When the NMI is input, the DMA transfer in progress
can be done in one transfer unit. Even if the NMI
interrupt is input while the DMAC is not in operation,
the NMIF bit is set to 1.
0: No NMI interrupt
1: NMI interrupt occurred
[Clearing condition]
•
Writing 0 after reading AE = 1*
Writing 0 after reading NMIF = 1*
CH5 > CH6 > CH7
CH6 > CH3 > CH7
Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 Sep. 28, 2009 Page 415 of 1650
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REJ09B0313-0300
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