R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 415

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

In the above conditions, a total of four conditions, that is, condition [1] or [2] (either one is
effective), condition [3] or [4] (either one is effective), a set of conditions [5] to [7] (these are
generated successively, and therefore the sum of them should be taken as one set of idle cycles),
and condition [8] are generated at the same time. The maximum number of idle cycles among
these four conditions become the number of idle cycles on the external bus. To ensure the
minimum idle cycles, be sure to make register settings for condition [1] or [2].
Note:
Previous access
CKIO
CSn
A total of four conditions (condition [1] or [2], condition [3] or [4], a set of conditions [5] to [7],
and condition [8]) generate idle cycle at the same time. Accordingly, the maximum number of
cycles among these four conditions become the number of idle cycles.
[1] DMAIW[2:0] setting in CMNCR
[2] IWW[2:0] setting in CSnBCR
[3] WTRP[1:0] setting in CSnWCR
[4] WM setting in CSnWCR
[5] Read
Idle cycle after access
IWRWD[2:0] setting in CSnBCR
IWRWS[2:0] setting in CSnBCR
IWRRD[2:0] setting in CSnBCR
IWRRS[2:0] setting in CSnBCR
TRWL[1:0] setting in CSnWCR
WTRC[1:0] setting in CSnWCR
data
transfer
Figure 9.53 Idle Cycle Conditions
[6] Internal bus idle cycles, etc.
External bus idle cycles
Idle cycle before access
Either one of them
is effective
Either one of them
is effective
[8] Idle cycles
Rev. 3.00 Sep. 28, 2009 Page 383 of 1650
between
different
memory types
[7] Write
Section 9 Bus State Controller (BSC)
data
wait
Condition [1] or [2]
Condition [3] or [4]
Set of conditions
[5] to [7]
Condition [8]
Next access
REJ09B0313-0300