R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 148
R0K572030S000BE
Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K572030S000BE
Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
- Current page: 148 of 1686
- Download datasheet (10Mb)
Section 4 Clock Pulse Generator (CPG)
4.5
The frequency of the internal clock (Iφ) and peripheral clock (Pφ) can be changed either by
changing the multiplication rate of PLL circuit or by changing the division rates of divider. All of
these are controlled by software through the frequency control register (FRQCR). The methods are
described below.
4.5.1
Oscillation settling time must be provided when the multiplication rate of the PLL circuit is
changed. The on-chip WDT counts the settling time. The oscillation settling time is the same as
when software standby mode is canceled.
1. In the initial state, the multiplication rate of PLL circuit is 8 time.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the IFC
4. This LSI pauses temporarily and the WDT starts incrementing. The internal and peripheral
5. Supply of the clock that has been set begins at WDT count overflow, and this LSI begins
Rev. 3.00 Sep. 28, 2009 Page 116 of 1650
REJ09B0313-0300
WDT. The following must be set:
WTCSR.TME = 0: WDT stops
WTCSR.CKS[2:0]: Division ratio of WDT count clock
WTCNT counter: Initial counter value
(The WDT count is incremented using the clock after the setting.)
and PFC2 to PFC0 bits.
clocks both stop and the WDT is supplied with the clock. The clock will continue to be output
at the CKIO pin. This state is the same as software standby mode. Whether or not registers are
initialized depends on the module. For details, see section 30.3, Register States in Each
Operating Mode.
operating again. The WDT stops after it overflows.
Changing the Frequency
Changing the Multiplication Rate
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