R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 841

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 16 Synchronous Serial Communication Unit (SSU)

Relationship between Data Input/Output Pins and Shift Register

The connection between data input/output pins and the SS shift register (SSTRSR) depends on the

combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 16.3

shows the relationship.

The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when

operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 16.3 (1)). The SSU

transmits serial data from the SSI pin and receives serial data from the SSO pin when operating

with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 16.3 (2)).

The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode

when operating with BIDE = 1 (bidirectional mode) (see figures 16.3 (3) and (4)).

However, even if both the TE and RE bits are set to 1, transmission and reception are not

performed simultaneously. Either the TE or RE bit must be selected.

The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when

operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function

as an input pin when MSS = 0 (see figures 16.3 (5) and (6)).

Rev. 3.00 Sep. 28, 2009 Page 809 of 1650

REJ09B0313-0300