R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 241
R0K572030S000BE
Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K572030S000BE
Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
- Current page: 241 of 1686
- Download datasheet (10Mb)
Bit
13
12
11 to 7
6
5
4 to 0
Bit Name
SCMFD0
SCMFD1
⎯
PCB1
PCB0
⎯
Initial
Value
All 0
All 0
0
0
0
0
R
R/W
R/W
R
R/W
R/W
R/W
Description
I Bus Cycle Condition Match Flag 0
When the I bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 0 does not
1: The I bus cycle condition for channel 0 matches
I Bus Cycle Condition Match Flag 1
When the I bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 1 does not
1: The I bus cycle condition for channel 1 matches
Reserved
These bits are always read as 0. The write value
should always be 0.
Selects the break timing of the instruction fetch cycle
for channel 1 as before or after instruction execution.
0: PC break of channel 1 is generated before
1: PC break of channel 1 is generated after instruction
Selects the break timing of the instruction fetch cycle
for channel 0 as before or after instruction execution.
0: PC break of channel 0 is generated before
1: PC break of channel 0 is generated after instruction
Reserved
These bits are always read as 0. The write value
should always be 0.
PC Break Select 1
PC Break Select 0
instruction execution
execution
instruction execution
execution
match
match
Rev. 3.00 Sep. 28, 2009 Page 209 of 1650
Section 7 User Break Controller (UBC)
REJ09B0313-0300
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