R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 469

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

(b)
In burst mode, once the DMAC obtains the bus mastership, it does not release the bus mastership
and continues to perform transfer until the transfer end condition is satisfied. In external request
mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the
bus mastership is passed to another bus master after the DMAC transfer request that has already
been accepted ends, even if the transfer end conditions have not been satisfied.
Figure 10.11 shows DMA transfer timing in burst mode.
(3)
Table 10.10 shows the relationship between request modes and bus modes by DMA transfer
category.
Table 10.10 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Address
Mode
Dual
Burst Mode
Relationship between Request Modes and Bus Modes by DMA Transfer Category
Transfer Category
External device with DACK and external
memory
External device with DACK and memory-
mapped external device
External memory and external memory
External memory and memory-mapped
external device
Memory-mapped external device and
memory-mapped external device
External memory and on-chip peripheral
module
Memory-mapped external device and
on-chip peripheral module
Bus cycle
DREQ
Figure 10.11 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)
CPU
CPU
CPU
DMAC DMAC DMAC DMAC
Read
Section 10 Direct Memory Access Controller (DMAC)
Write
Request
Mode
External
External
All*
All*
All*
All*
All*
Read
4
4
4
1
1
Rev. 3.00 Sep. 28, 2009 Page 437 of 1650
Write
Bus
Mode
B/C
B/C
B/C
B/C
B/C
B/C*
B/C*
5
5
CPU
Transfer
Size (Bits)
8/16/32/128
8/16/32/128
8/16/32/128
8/16/32/128
8/16/32/128
8/16/32/128*
8/16/32/128*
CPU
REJ09B0313-0300
2
2
Usable
Channels
0 to 3
0 to 3
0 to 7*
0 to 7*
0 to 7*
0 to 7*
0 to 7*
3
3
3
3
3