R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 495

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
11.3.2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register
settings should be changed only when TCNT operation is stopped.
Bit
7
6
Bit Name
BFE
Timer Mode Register (TMDR)
Initial value:
Initial
Value
0
0
R/W:
Bit:
R
7
0
-
R/W
R
R/W
R/W
BFE
6
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Buffer Operation E
Specifies whether TGRE_0 and TGRF_0 are to operate
in the normal way or to be used together for buffer
operation.
TGRF compare match is generated when TGRF is
used as the buffer register.
In channels 1 to 4, this bit is reserved. It is always read
as 0 and the write value should always be 0.
0: TGRE_0 and TGRF_0 operate normally
1: TGRE_0 and TGRF_0 used together for buffer
R/W
BFB
5
0
operation
R/W
BFA
4
0
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
3
0
Rev. 3.00 Sep. 28, 2009 Page 463 of 1650
R/W
2
0
MD[3:0]
R/W
1
0
R/W
0
0
REJ09B0313-0300

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