R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 104

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 2 CPU
The table below shows the format of instruction codes, operation, and execution states. They are
described by using this format according to their classification.
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In
Rev. 3.00 Sep. 28, 2009 Page 72 of 1650
REJ09B0313-0300
Instruction
Indicated by mnemonic.
[Legend]
Rm: Source register
Rn:
imm: Immediate data
disp: Displacement*
Destination register
2. Depending on the operand size, displacement is scaled by ×1, ×2, or ×4. For details,
practice, the number of instruction execution states will be increased in cases such as
the following:
a. When there is a conflict between an instruction fetch and a data access
refer to the SH-2A, SH2A-FPU Software Manual.
b. When the destination register of a load instruction (memory → register) is the same
as the register used by the next instruction.
2
Instruction Code
Indicated in MSB ↔
LSB order.
[Legend]
mmmm: Source register
nnnn: Destination register
iiii:
dddd:
0000: R0
0001: R1
.........
1111: R15
Immediate data
Displacement
Operation
Indicates summary of
operation.
[Legend]
→, ←:
(xx):
M/Q/T: Flag bits in SR
&:
|:
^:
~:
<<n: n-bit left shift
>>n: n-bit right shift
Logical AND of each bit
Logical OR of each bit
Exclusive logical OR of
each bit
Logical NOT of each bit
Transfer direction
Memory operand
Execution
States
Value when no
wait states are
inserted. *
1
T Bit
Value of T bit after
instruction is
executed.
Explanation of
Symbols
—: No change