R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 610

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(n)
Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing
occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change
in duty cycle at synchronous counter clearing.
Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval
at the trough as indicated by (10) or (11) in figure 11.56. When synchronous clearing occurs
outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb
interval at the trough, if synchronous clearing occurs in the initial value output period (indicated
by (1) in figure 11.56) immediately after the counters start operation, initial value output is not
suppressed.
Negative phase
Rev. 3.00 Sep. 28, 2009 Page 578 of 1650
REJ09B0313-0300
Positive phase
Counter start
TGRA_3
TGRB_3
Output Waveform Control at Synchronous Counter Clearing in Complementary PWM
Mode
H'0000
TCDR
TDDR
Tb interval
(1)
Figure 11.56 Timing for Synchronous Counter Clearing
(2)
(3)
(4)
Tb interval
(5)
(6)
(7)
(8)
(9)
Tb interval
(10) (11)
Output waveform is active-low
TCNT_3
TCNT_4

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