R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 892

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 17 I

In slave receive mode, the master device outputs the transmit clock and transmit data, and the

slave device returns an acknowledge signal. For slave receive mode operation timing, refer to

figures 17.11 and 17.12. The reception procedure and operations in slave receive mode are

described below.

1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and

2. When the slave address matches in the first frame following detection of the start condition,

3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is

4. The last byte data is read by reading ICDRR.

Rev. 3.00 Sep. 28, 2009 Page 860 of 1650

REJ09B0313-0300

(Master output)

(Slave output)

TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches.

the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th

clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the

read data show the slave address and R/W, it is not used.)

fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be

returned to the master device, is reflected to the next transmit frame.

Slave Receive Operation

C Bus Interface 3 (IIC3)

Figure 17.11 Slave Receive Mode Operation Timing (1)

[2] Read ICDRR (dummy read)

[2] Read ICDRR