R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1145

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Table 23.4 Test Mode Operation
23.3.5
CFBCFG, D0FBCFG, and D1FBCFG are registers that control FIFO port accesses. There are
three FIFO ports; CPU-FIFO, DMA0-FIFO, and DMA1-FIFO. Accesses to these ports are
controlled by the corresponding configuration registers.
These registers are initialized by a power-on reset.
Initial value:
Test Mode
Normal operation
Test_J
Test_K
Test_SE0_NAK
Test_Packet
Reserved
Bit
15 to 10 ⎯
9
R/W:
Bit:
FIFO Port Configuration Registers (CFBCFG, D0FBCFG, D1FBCFG)
Bit Name
TENDE
15
R
0
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
0
12
R
0
-
11
R
0
Functions of Function
Controller Selected
0000
0001
0010
0011
0100
0101 to 0111
-
R/W
R
R/W
10
R
0
-
TENDE FEND
R/W
9
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Transfer End Sampling Enable
Controls the acceptance of a DMA transfer end
signal sent from the direct memory access controller
(DMAC) at the end of DMA transfer.
0: A DMA transfer end signal is not sampled.
1: A DMA transfer end signal is sampled.
R/W
8
0
Section 23 USB 2.0 Host/Function Module (USB)
R
7
0
-
UTST Bit Setting
Rev. 3.00 Sep. 28, 2009 Page 1113 of 1650
R
6
0
-
Functions of Host Controller
Selected
0000
1001
1010
1011
1100
1101 to 1111
R
5
0
-
R
4
0
-
RW
3
1
REJ09B0313-0300
R/W
FWAIT[3:0]
2
1
R/W
1
1
R/W
0
1