R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 249

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

7.5
1. The CPU can read from or write to the UBC registers via the internal CPU bus. Accordingly,
2. The UBC cannot monitor the C bus, internal CPU, and internal DMA bus cycles in the same
3. When a user break interrupt request and another exception source occur at the same
4. Note the following when a break occurs in a delay slot.
5. User breaks are disabled during UBC module standby mode. Do not read from or write to the
6. Do not set an address within an interrupt exception handling routine whose interrupt priority
7. Do not set break after instruction execution for the SLEEP instruction or for the delayed
8. When setting a break for a 32-bit instruction, set the address where the upper 16 bits are
9. Do not set a user break before instruction execution for the instruction following the DIVU or
during the period from executing an instruction to rewrite the UBC register till the new value
is actually rewritten, the desired break may not occur. In order to know the timing when the
UBC register is changed, read from the last written register. Instructions after then are valid for
the newly written register value.
channel.
instruction, which has higher priority is determined according to the priority levels defined in
table 5.1 in section 5, Exception Handling. If an exception source with higher priority occurs,
the user break interrupt request is not received.
If a pre-execution break is set at a delay slot instruction, the user break interrupt request is not
received immediately before execution of the branch destination.
UBC registers during UBC module standby mode; the values are not guaranteed.
level is at least 15 (including user break interrupts) as a break address.
branch instruction where the SLEEP instruction is placed at its delay slot.
placed. If the address of the lower 16 bits is set and a break before instruction execution is set
as a break condition, the break is handled as a break after instruction execution.
DIVS instruction. If a user break before instruction execution is set for the instruction
following the DIVU or DIVS instruction and an exception or interrupt occurs during execution
of the DIVU or DIVS instruction, a user break occurs before instruction execution even though
execution of the DIVU or DIVS instruction is halted.
Usage Notes
Rev. 3.00 Sep. 28, 2009 Page 217 of 1650
Section 7 User Break Controller (UBC)
REJ09B0313-0300