R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 546

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.22 Timer Dead Time Data Register (TDDR)
TDDR is a 16-bit register, used only in complementary PWM mode that specifies the TCNT_3
and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and
TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the
TCNT_3 counter and the count operation starts.
The initial value of TDDR is H'FFFF.
Initial value:
11.3.23 Timer Cycle Data Register (TCDR)
TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync
value as the TCDR register value. This register is constantly compared with the TCNTS counter in
complementary PWM mode, and when a match occurs, the TCNTS counter switches direction
(decrement to increment).
The initial value of TCDR is H'FFFF.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 514 of 1650
REJ09B0313-0300
Note:
Note:
R/W:
R/W:
Bit:
Bit:
Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units.
Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units.
R/W
R/W
15
15
1
1
R/W
R/W
14
14
1
1
R/W
R/W
13
13
1
1
R/W
R/W
12
12
1
1
R/W
R/W
11
11
1
1
R/W
R/W
10
10
1
1
R/W
R/W
9
1
9
1
R/W
R/W
8
1
8
1
R/W
R/W
7
1
7
1
R/W
R/W
6
1
6
1
R/W
R/W
5
1
5
1
R/W
R/W
4
1
4
1
R/W
R/W
3
1
3
1
R/W
R/W
2
1
2
1
R/W
R/W
1
1
1
1
R/W
R/W
0
1
0
1