R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 401

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
(1)
Figure 9.42 shows the basic timing of the PCMCIA IC memory card interface. When areas 5 and 6
are specified as the PCMCIA interface, the bus is accessed with the IC memory card interface
according to the SA[1:0] bit settings in CS5WCR and CS6WCR. If the external bus frequency
(CKIO) increases, the setup times and hold times for the address pins (A25 to A0), card enable
signals (CE1A, CE2A, CE1B, CE2B), and write data (D15 to D0) to the RD and WE signals
become insufficient. To prevent this error, this LSI enables the setup times and hold times for
areas 5 and 6 to be specified independently, using CS5WCR and CS6WCR. In the PCMCIA
interface, as in the normal space interface, a software wait or hardware wait using the WAIT pin
can be inserted. Figure 9.43 shows the PCMCIA memory bus wait timing.
Read
Write
Basic Timing for Memory Card Interface
Figure 9.42 Basic Access Timing for PCMCIA Memory Card Interface
D15 to D0
A25 to A0
D15 to D0
RD/WR
CExx
CKIO
WE
RD
BS
Tpcm1
Tpcm1w
Tpcm1w
Rev. 3.00 Sep. 28, 2009 Page 369 of 1650
Section 9 Bus State Controller (BSC)
Tpcm1w
Tpcm2
REJ09B0313-0300

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