R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 627

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

• Basic Operation Example of A/D Converter Start Request Delaying Function
• Buffer Transfer
• A/D Converter Start Request Delaying Function Linked with Interrupt Skipping
Figure 11.74 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation
A/D converter start request
Figure 11.74 shows a basic example of A/D converter request signal (TRG4AN) operation
when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter
start request signal is output during TCNT_4 down-counting.
The data in the timer A/D converter start request cycle set registers (TADCORA_4 and
TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set
buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer
registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits
in the timer A/D converter start request control register (TADCR_4).
A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with
interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
the timer A/D converter start request control register (TADCR).
Figure 11.75 shows an example of A/D converter start request signal (TRG4AN) operation
when TRG4AN output is enabled during TCNT_4 up-counting and down-counting and A/D
converter start requests are linked with interrupt skipping.
Figure 11.76 shows another example of A/D converter start request signal (TRG4AN)
operation when TRG4AN output is enabled during TCNT_4 up-counting and A/D converter
start requests are linked with interrupt skipping.
TADCOBRA_4
TADCORA_4
Transfer from cycle buffer
register to cycle register
(TRG4AN)
Transfer from cycle buffer
register to cycle register
TCNT_4
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 3.00 Sep. 28, 2009 Page 595 of 1650
Transfer from cycle buffer
register to cycle register
(Complementary PWM mode)
REJ09B0313-0300