R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 566

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

The timing for transfer from buffer registers to timer general registers can be selected in PWM

mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation

transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match (initial

setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as transfer

timing is one of the following cases.

• When TCNT overflows (H'FFFF to H'0000)

• When H'0000 is written to TCNT during counting

• When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits

Note: TBTM must be modified only while TCNT stops.

Figure 11.19 shows an operation example in which PWM mode 1 is designated for channel 0 and

buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are

TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare

match B. The TTSA bit in TBTM_0 is set to 1.

Rev. 3.00 Sep. 28, 2009 Page 534 of 1650

REJ09B0313-0300

Selecting Timing for Transfer from Buffer Registers to Timer General Registers in

Buffer Operation

Figure 11.18 Example of Buffer Operation (2)