R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 476

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 10 Direct Memory Access Controller (DMAC)
10.5
10.5.1
When executing DMA transfer by reload function of DMAC, setting different value to DMA
reload transfer count register (RDMATCR_n) from the DMA transfer count register
(DMATCR_n) value set when transfer is started lead to an error in the operation of the half end
flag of DMA channel control register (CHCR_n). Even though the value of DMATCR_n is
rewritten by reload operation, half end flag is set based on the value set when transfer is started.
Because of this, there may be errors where (a) the set timing of the half end flag is not correct, or
(b) the half end flag can not be set, may be generated. When executing DMA transfer by reload
function under the condition that different values are set to RDMATCR_n from DMATCR_n, do
not use half end flag or half end interrupt.
10.5.2
When the external memory is the MPX-I/O or burst MPX-I/O, the DACK output is asserted with
the timing of the data cycle. For details, see the respective figures in section 9.5.5, MPX-I/O
Interface, or section 9.5.10, Burst MPX-I/O Interface.
When the memory is other than the MPX-I/O or burst MPX-I/O, the DACK output is asserted
with the same timing as the corresponding CS signal.
The TEND output does not depend on the type of memory and is always asserted with the same
timing as the corresponding CS signal.
Rev. 3.00 Sep. 28, 2009 Page 444 of 1650
REJ09B0313-0300
Usage Notes
Setting of the Half-End Flag and Generation of the Half-End Interrupt
Timing of DACK and TEND Outputs