R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 565

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Figure 11.17 shows an operation example in which PWM mode 1 has been designated for channel

0, and buffer operation has been designated for TGRA and TGRC. The settings used in this

example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at

compare match B. In this example, the TTSA bit in TBTM is cleared to 0.

As buffer operation has been set, when compare match A occurs the output changes and the value

in buffer register TGRC is simultaneously transferred to timer general register TGRA. This

operation is repeated each time that compare match A occurs.

For details of PWM modes, see section 11.4.5, PWM Modes.

Figure 11.18 shows an operation example in which TGRA has been designated as an input capture

Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges

have been selected as the TIOCA pin input capture input edge.

As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of

input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.

Examples of Buffer Operation

When TGR is an output compare register

When TGR is an input capture register

Figure 11.17 Example of Buffer Operation (1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 3.00 Sep. 28, 2009 Page 533 of 1650

REJ09B0313-0300