R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1154

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 23 USB 2.0 Host/Function Module (USB)
Notes: 1. Only 1 can be written to.
Rev. 3.00 Sep. 28, 2009 Page 1122 of 1650
REJ09B0313-0300
Bit
15
14
13
12
11 to 0
2. Only reading 0 and writing 1 are valid.
3. The BCLR bit is only valid for the buffer memory on the CPU side when a pipe other
4. The DTLN bits are only valid for the buffer memory on the CPU side. Confirm that
Bit Name
BVAL
BCLR
FRDY
⎯
DTLN[11:0]
than DCP has been selected. Set BCLR to 1 after confirming that FRDY is 1. When
DCP is selected as a pipe, the buffer memory on the SIE side is also cleared. In this
case, confirming that FRDY = 1 is not necessary.
FRDY = 1 before checking the DTLN bit.
Initial
Value
0
0
0
0
H'000
R/W
R/W*
R/W*
R
R
R
1
2
Description
Buffer Memory Valid Flag
Writing 1 to this bit is valid when the direction of data
packet is the transmitting direction (when data is
being written to the buffer memory). When the
direction is set to the receiving direction, this bit
should be cleared to 0.
0: Invalid
1: Writing ended
CPU Buffer Clear*
This bit should be used to clear the buffer with this bit
with the pipe invalid state by the pipe configuration
(PID = NAK).
0: Invalid
1: Clears the buffer memory on the CPU side.
FIFO Port Ready
Confirming the FIFO port state by reading this bit
requires an access cycle of at least 450 ns after the
pipe has been selected.
0: FIFO port access is disabled.
1: FIFO port access is enabled.
Reserved
This bit is always read as 0. The write value should
always be 0.
Receive Data Length*
The length of the receive data can be confirmed.
3
4