R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1290
R0K572030S000BE
Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K572030S000BE
Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
- Current page: 1290 of 1686
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Section 24 LCD Controller (LCDC)
Rev. 3.00 Sep. 28, 2009 Page 1258 of 1650
REJ09B0313-0300
Bit
12
11
10
Bit Name
VEINTEN
MINTS
FINTS
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Vsync Ending Point Interrupt Enable
Enables or disables the generation of an interrupt at the
end point of LCDC's Vsync.
0: Interrupt at the end point of the Vsync signal is
1: Interrupt at the end point of the Vsync signal is
Memory Access Interrupt State
Indicates the memory access interrupt handling state.
This bit indicates 1 when the LCDC memory access
interrupt is generated (set state). During the memory
access interrupt handling routine, this bit should be
cleared by writing 0.
0: LCDC did not generate a memory access interrupt or
1: LCDC has generated a memory access end interrupt
Flame End Interrupt State
Indicates the flame end interrupt handling state.
This bit indicates 1 at the time when the LCDC flame
end interrupt is generated (set state). During the flame
end interrupt handling routine, this bit should be cleared
by writing 0.
0: LCDC did not generate a flame end interrupt or has
1: LCDC has generated a flame end interrupt and not
disabled
has been informed that the generated memory
access interrupt has completed
and not yet been informed that the generated
memory access interrupt has completed
been informed that the generated flame end interrupt
has completed
yet been informed that the generated flame end
interrupt has completed
enabled
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