R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 848

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 Sep. 28, 2009 Page 816 of 1650
REJ09B0313-0300
[1]
[2]
[3]
[4]
Confirm that the TEND bit is cleared to 0
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
Write transmit data to SSTDR
Clear the TE bit in SSER to 0
Read the TDRE bit in SSSR
TDRE automatically cleared
Read the TEND bit in SSSR
Consecutive data transmission?
Clear the TEND bit to 0
Figure 16.6 Flowchart Example of Data Transmission (SSU Mode)
quantum elapsed?
End transmission
Initial setting
One bit time
TDRE = 1?
TEND = 1?
Yes
Yes
Yes
No
Start
Yes
No
No
No
[1] Initial setting:
[2] Check that the SSU state and write transmit data:
[3] Procedure for consecutive data transmission:
[4] Procedure for data transmission end:
Specify the transmit data format.
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
To continue data transmission, confirm that the TDRE bit is 1
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
Note: Hatching boxes represent SSU internal operations.