R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 544

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 3.00 Sep. 28, 2009 Page 512 of 1650
REJ09B0313-0300
Bit
5
4
3
2
1
0
Bit Name
N
P
FB
WF
VF
UF
Initial
value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reverse Phase Output (N) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while
the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are
output.
0: Level output
1: Reset synchronized PWM/complementary PWM
Positive Phase Output (P) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while
the positive pin (TIOC3B, TIOC4A, and TIOC4B) are
output.
0: Level output
1: Reset synchronized PWM/complementary PWM
External Feedback Signal Enable
This bit selects whether the switching of the output of
the positive/reverse phase is carried out automatically
with the MTU2/channel 0 TGRA, TGRB, TGRC input
capture signals or by writing 0 or 1 to bits 2 to 0 in
TGCR.
0: Output switching is external input (Input sources are
1: Output switching is carried out by software (setting
Output Phase Switch 2 to 0
These bits set the positive phase/negative phase output
phase on or off state. The setting of these bits is valid
only when the FB bit in this register is set to 1. In this
case, the setting of bits 2 to 0 is a substitute for external
input. See table 11.37.
output
output
channel 0 TGRA, TGRB, TGRC input capture signal)
values of UF, VF, and WF in TGCR).