R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 46

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 1 Overview
Rev. 3.00 Sep. 28, 2009 Page 14 of 1650
REJ09B0313-0300
Classification
Interrupts
Address bus
Data bus
Bus control
Symbol
NMI
IRQ7 to IRQ0
PINT7 to PINT0 I
IRQOUT
A25 to A0
D31 to D0
CS7 to CS0
RD
RD/WR
BS
AH
FRAME
WAIT
WE0
I/O
I
I
O
O
I/O
O
O
O
O
O
O
I
O
Name
Non-maskable
interrupt
Interrupt requests
7 to 0
Interrupt requests
7 to 0
Interrupt request
output
Address bus
Data bus
Chip select 7 to 0 Chip-select signals for external
Read
Read/write
Bus start
Address hold
FRAME signal
Wait
Byte select
Function
Non-maskable interrupt request pin.
Fix it high when not in use.
Maskable interrupt request pins.
Level-input or edge-input detection
can be selected. When the edge-
input detection is selected, the rising
edge, falling edge, or both edges can
also be selected.
Maskable interrupt request pins.
Only level-input detection can be
selected.
Indicates that an interrupt has
occurred, enabling external devices
to be informed of an interrupt
occurrence even while the bus
mastership is released.
memory or devices.
Indicates that data is read from an
external device.
device that uses the address/data-
multiplexed bus.
Connected to the FRAME signal in
the burst MPX-I/O interface.
cycles during access to the external
space.
Indicates a write access to bits 7 to 0
of data of external memory or
device.
Outputs addresses.
Bidirectional data bus.
Read/write signal.
Bus-cycle start signal.
Address hold timing signal for the
Inserts a wait cycle into the bus