R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 418

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 9 Bus State Controller (BSC)
Rev. 3.00 Sep. 28, 2009 Page 386 of 1650
REJ09B0313-0300
Sample Estimation of Idle Cycles between Access Cycles
This example estimates the idle cycles for data transfer from the CS1 space to CS2 space by CPU access. Transfer is
repeated in the following order: CS1 read → CS1 read → CS2 write → CS2 write → CS1 read → ...
• Conditions
The idle cycles generated under each condition are estimated for each pair of access cycles. In the following table,
R indicates a read cycle and W indicates a write cycle.
The bits for setting the idle cycles between access cycles in CS1BCR and CS2BCR are all set to 0.
(CS negation is not extended).
also 32 bits.
In CS1WCR and CS2WCR, the WM bit is set to 1 (external WAIT pin disabled) and the HW[1:0] bits are set to 00
Iφ:Bφ is set to 4:1, and no other processing is done during transfer.
For both the CS1 and CS2 spaces, normal SRAM devices are connected, the bus width is 32 bits, and access size is
[1] or [2]
[3] or [4]
[5]
[6]
[7]
[5] + [6] + [7]
[8]
Estimated idle
cycles
Actual idle
cycles
Condition
Figure 9.54 Comparison between Estimated Idle Cycles and Actual Value
R → R
0
0
1
0
0
1
0
1
1
R → W
0
0
1
2
1
4
0
4
4
W → W
0
0
0
2
0
2
0
2
2
W → R
0
0
0
0
0
0
0
0
1
CSnBCR is set to 0.
The WM bit is set to 1.
Generated after a read cycle.
See the Iφ:Bφ = 4:1 columns in table 8.19.
No idle cycle is generated for the second time due to the
write buffer effect.
Value for SRAM → SRAM access
Maximum value among conditions [1] or [2], [3] or [4],
[5] + [6] + [7], and [8]
The estimated value does not match the actual value in
the W → R cycles because the internal idle cycles due to
condition [6] is estimated as 0 but actually an internal idle
cycle is generated due to execution of a loop condition
check instruction.
Note