R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 210

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 6 Interrupt Controller (INTC)
6.6
6.6.1
The sequence of interrupt operations is described below. Figure 6.2 shows the operation flow.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
3. The priority level of the interrupt selected by the interrupt controller is compared with the
4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin.
5. The CPU detects the interrupt request sent from the interrupt controller when the CPU decodes
6. The interrupt exception service routine start address is fetched from the exception handling
7. The status register (SR) is saved onto the stack, and the priority level of the accepted interrupt
8. The program counter (PC) is saved onto the stack.
9. The CPU jumps to the fetched interrupt exception service routine start address and starts
10. A high level is output from the IRQOUT pin. However, if the interrupt controller accepts an
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following the priority levels set in interrupt priority registers 01, 02, and 05 to 17 (IPR01,
IPR02, and IPR05 to IPR17). Lower priority interrupts are ignored*. If two of these interrupts
have the same priority level or if multiple interrupts occur within a single IPR, the interrupt
with the highest priority is selected, according to the default priority and IPR setting unit
internal priority shown in table 6.4.
interrupt level mask bits (I3 to I0) in the status register (SR) of the CPU. If the interrupt
request priority level is equal to or less than the level set in bits I3 to I0, the interrupt request is
ignored. If the interrupt request priority level is higher than the level in bits I3 to I0, the
interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU.
the instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception handling (figure 6.4).
vector table corresponding to the accepted interrupt.
is copied to bits I3 to I0 in SR.
executing the program. The jump that occurs is not a delayed branch.
interrupt with a higher priority than the interrupt just being accepted, the IRQOUT pin holds
low level.
Operation
Interrupt Operation Sequence