R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1071

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

20.5
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
An ADI interrupt request is generated if the ADIE bit is set to 1 when the ADF bit in ADCSR is
set to 1 on completion of A/D conversion. Note that the direct memory access controller (DMAC)
can be activated by an ADI interrupt depending on the DMAC setting. In this case, an interrupt is
not issued to the CPU. If the setting to activate the DMAC has not been made, an interrupt request
is sent to the CPU. Having the converted data read by the DMAC in response to an ADI interrupt
enables continuous conversion to be achieved without imposing a load on software.
In single mode, set the DMAC so that DMA transfer initiated by an ADI interrupt is performed
only once. In the case of A/D conversion on multiple channels in scan mode or multi mode, setting
the DMA transfer count to one causes DMA transfer to finish after transferring only one channel
of data. To make the DMAC transfer all conversion data, set the ADDR where A/D conversion
data is stored as the transfer source address, set the number of converted channels as the transfer
count, and set the TC bit in the DMA channel control register (CHCR) to 1.
When the DMAC is activated by ADI, the ADF bit in ADCSR is automatically cleared to 0 when
data is transferred by the DMAC.
Table 20.6 Relationship between Interrupt Sources and DMAC Transfer Request
Name
ADI
Interrupt Sources and DMAC Transfer Request
Interrupt Source
A/D conversion end
Interrupt Flag
ADF in ADCSR
Rev. 3.00 Sep. 28, 2009 Page 1039 of 1650
Section 20 A/D Converter (ADC)
DMAC Activation
Possible
REJ09B0313-0300