R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 766

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 734 of 1650
REJ09B0313-0300
Bit
4
3
Bit Name
RE
REIE
Initial
Value
0
0
R/W
R/W
R/W
Description
Receive Enable
Enables or disables the serial receiver.
0: Receiver disabled*
1: Receiver enabled*
Notes: 1. Clearing RE to 0 does not affect the receive
Enables or disables the receive-error (ERI) interrupts
and break (BRI) interrupts. The setting of REIE bit is
valid only when RIE bit is set to 0.
0: Receive-error interrupt (ERI) and break interrupt
1: Receive-error interrupt (ERI) and break interrupt
Note:
Receive Error Interrupt Enable
(BRI) requests are disabled
(BRI) requests are enabled*
2. Serial reception starts when a start bit is
*
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
detected in asynchronous mode, or
synchronous clock is detected in clock
synchronous mode. Select the receive format
in SCSMR and SCFCR and reset the receive
FIFO before setting RE to 1.
ERI or BRI interrupt requests can be
cleared by reading the ER, BR or ORER
flag after it has been set to 1, then clearing
the flag to 0, or by clearing RIE and REIE to
0. Even if RIE is set to 0, when REIE is set
to 1, ERI or BRI interrupt requests are
enabled. Set so If SCIF wants to inform
INTC of ERI or BRI interrupt requests
during DMA transfer.
2
1