R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 16

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

9.5
9.6
Section 10 Direct Memory Access Controller (DMAC)...................................393
10.1 Features.............................................................................................................................. 393
10.2 Input/Output Pins............................................................................................................... 396
10.3 Register Descriptions ......................................................................................................... 397
10.4 Operation ........................................................................................................................... 421
10.5 Usage Notes ....................................................................................................................... 444
Rev. 3.00 Sep. 28, 2009 Page xiv of xxx
REJ09B0313-0300
9.4.7
Operation ........................................................................................................................... 297
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
9.5.9
9.5.10 Burst MPX-I/O Interface ...................................................................................... 374
9.5.11 Burst ROM (Clocked Synchronous) Interface...................................................... 379
9.5.12 Wait between Access Cycles ................................................................................ 380
9.5.13 Bus Arbitration ..................................................................................................... 387
9.5.14 Others.................................................................................................................... 389
Usage Notes ....................................................................................................................... 391
9.6.1
10.3.1 DMA Source Address Registers (SAR)................................................................ 401
10.3.2 DMA Destination Address Registers (DAR)........................................................ 402
10.3.3 DMA Transfer Count Registers (DMATCR) ....................................................... 402
10.3.4 DMA Channel Control Registers (CHCR) ........................................................... 403
10.3.5 DMA Reload Source Address Registers (RSAR) ................................................. 411
10.3.6 DMA Reload Destination Address Registers (RDAR) ......................................... 412
10.3.7 DMA Reload Transfer Count Registers (RDMATCR) ........................................ 413
10.3.8 DMA Operation Register (DMAOR) ................................................................... 414
10.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3).................. 418
10.4.1 Transfer Flow........................................................................................................ 421
10.4.2 DMA Transfer Requests ....................................................................................... 423
10.4.3 Channel Priority.................................................................................................... 428
10.4.4 DMA Transfer Types............................................................................................ 431
10.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing .................................... 440
Refresh Time Constant Register (RTCOR) .......................................................... 296
Endian/Access Size and Data Alignment.............................................................. 297
Normal Space Interface ........................................................................................ 304
Access Wait Control ............................................................................................. 309
CSn Assert Period Expansion ............................................................................... 311
MPX-I/O Interface................................................................................................ 312
SDRAM Interface ................................................................................................. 316
Burst ROM (Clocked Asynchronous) Interface.................................................... 360
SRAM Interface with Byte Selection ................................................................... 362
PCMCIA Interface................................................................................................ 367
Note when using both the bus arbitration function and
the software standby mode ................................................................................... 391