R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 836

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 16 Synchronous Serial Communication Unit (SSU)
16.3.6
SSCR2 is a register that selects the assert timing of the SCS pin, data output timing of the SSO
pin, and set timing of the TEND bit.
Rev. 3.00 Sep. 28, 2009 Page 804 of 1650
REJ09B0313-0300
Bit
7 to 5
4
3
2
1, 0
Bit Name
⎯
TENDSTS 0
SCSATS
SSODTS
⎯
SS Control Register 2 (SSCR2)
Initial value:
Initial
Value
All 0
0
0
All 0
R/W:
Bit:
R/W
R
R/W
R/W
R/W
R
R
7
0
-
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
and master mode).
0: Sets the TEND bit when the last bit is being
1: Sets the TEND bit after the last bit is transmitted
SSU and master mode).
0: Min. values of t
1: Min. values of t
Selects the data output timing of the SSO pin (valid in
SSU and master mode)
0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
Reserved
These bits are always read as 0. The write value should
always be 0.
Selects the timing of setting the TEND bit (valid in SSU
Selects the assertion timing of the SCS pin (valid in
R
5
0
-
transmitted
= 1, TE = 1, and RE = 0, the SSO pin outputs data
= 1, TE = 1, and RE = 0, the SSO pin outputs data
while the SCS pin is driven low
TENDSTS
R/W
4
0
SCSATS SSODTS
R/W
3
0
LEAD
LEAD
R/W
2
0
and t
and t
R
1
0
-
LAG
LAG
are 1/2 × t
are 3/2 × t
R
0
0
-
SUcyc
SUcyc