R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1232

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 23 USB 2.0 Host/Function Module (USB)
(b)
Table 23.17 shows the clearing of the buffer memory by this module. The buffer memory can be
cleared using the four bits indicated below.
Table 23.17 List of Buffer Clearing Methods
(c)
Table 23.18 shows the FIFO buffer memory map of this controller. The buffer memory has special
fixed areas to which pipes are assigned in advance, and user areas that can be set by the user.
The buffer for the DCP is a special fixed area that is used both for control read transfers and
control write transfers.
The PIPE6 and PIPE7 area is assigned in advance, but the area for pipes that are not being used
can be assigned to PIPE1 to PIPE5 as a user area.
The settings should ensure that the various pipes do not overlap. Note that each area is twice as
large as the setting value in the double buffer.
Also, the buffer size should not be specified using a value that is less than the maximum packet
size.
Rev. 3.00 Sep. 28, 2009 Page 1200 of 1650
REJ09B0313-0300
Bit Name
Register
Function
Clearing
method
Buffer Clearing
Buffer Areas
BCLR
CFIFOCTR
DnFIFOCTR
Clears the buffer
memory on the CPU
side
Cleared by writing 1 Cleared by writing 1 1: Mode valid
SCLR
CFIFOSIE
Clears the buffer
memory on the SIE
side
DCLRM
DnFIFOSEL
In this mode, after
the data of the
specified pipe has
been read, the
buffer memory is
cleared
automatically.
0: Mode invalid
ACLRM
PIPEnCTR
This is the auto
buffer clear mode, in
which all of the
received packets
are destroyed.
1: Mode valid
0: Mode invalid