MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MC68Hc912D60A
MC68HC912D60C
MC68HC912D60P
Technical Data
HC12
Microcontrollers
MC68HC912D60A/D
Rev. 3.1
08/2005
freescale.com

MC912D60CCPVE Summary of contents

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MC68Hc912D60A MC68HC912D60C MC68HC912D60P Technical Data HC12 Microcontrollers MC68HC912D60A/D Rev. 3.1 08/2005 freescale.com ...

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... Freescale was negligent regarding the design or manufacture of the part. Freescale, Inc Equal Opportunity/Affirmative Action Employer. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor © Freescale, Inc., 2005 Technical Data 3 ...

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... Technical Data 4 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... Section 10. I/O Ports with Key Wake- 129 Section 11. Clock Functions . . . . . . . . . . . . . . . . . . . . . 137 Section 12. Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Section 13. Pulse Width Modulator . . . . . . . . . . . . . . . . 207 Section 14. Enhanced Capture Timer . . . . . . . . . . . . . . 223 Section 15. Multiple Serial Interface . . . . . . . . . . . . . . . 263 Section 16. Freescale Interconnect Bus . . . . . . . . . . . . 289 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor List of Paragraphs List of Paragraphs Technical Data 5 ...

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... Section 19. Development Support 377 Section 20. Electrical Specifications 405 Section 21. Appendix: CGM Practical Aspects . . . . . . 427 Section 22. Appendix: Changes from MC68HC912D60437 Section 23. Appendix: Information on MC68HC912D60A Mask Set Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Glossary 447 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Technical Data 6 List of Paragraphs MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Technical Data — List of Paragraphs Technical Data — Table of Contents Technical Data — List of Figures Technical Data — List of Tables Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Devices Covered in this Document Features ...

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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Register Block Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Internal Resource Mapping .77 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Section 6. Bus Control and Input/Output Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Detecting Access Type from External Signals . . . . . . . . . . . . . 85 Registers .86 Section 7. Flash Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Table of Contents MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Overview .98 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . . 98 Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . 101 Erasing the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Flash protection bit FPOPEN ...

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... Phase-Locked Loop (PLL 139 Acquisition and Tracking Modes 141 Limp-Home and Fast STOP Recovery modes . . . . . . . . . . . . 143 System Clock Frequency formulas . . . . . . . . . . . . . . . . . . . . . 162 Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Computer Operating Properly (COP 166 Section 12. Oscillator Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Table of Contents MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 MC68HC912D60A Oscillator Specification 176 MC68HC912D60C Colpitts Oscillator Specification . . . . . . . . 179 MC68HC912D60P Pierce Oscillator Specification . . . . . . . . . 194 Section 13. Pulse Width Modulator Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 PWM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 PWM Boundary Cases ...

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... External Pins 304 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .310 Interrupts .314 Protocol Violation Protection 316 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Section 18. Analog-to-Digital Converter Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Table of Contents MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... Section 22. Appendix: Changes from MC68HC912D60 22.1 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 ATD Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 ATD Operation In Different MCU Modes . . . . . . . . . . . . . . . . 355 General Purpose Digital Input Port Operation . . . . . . . . . . . . 357 Application Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .358 ATD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Section 19 ...

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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Flash Protection Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Clock Circuitry 444 Pseudo Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 Oscillator .444 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Technical Data — Glossary Technical Data — Revision History Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457 Changes from Rev 2.0 to Rev 3 457 Table of Contents MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... Block Diagram of PWM Center-Aligned Output Channel . . . . 209 13-3 PWM Clock Sources 210 14-1 Timer Block Diagram in Latch Mode .225 14-2 Timer Block Diagram in Queue Mode 226 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Title MC68HC912D60A 112-pin QFP Block Diagram . . . . . . . . . . . 29 MC68HC912D60A 80-pin QFP Block Diagram . . . . . . . . . . . . 30 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pin Assignments in 112-pin TQFP for MC68HC912D60A ...

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... STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 416 20-4 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 417 20-5 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 20-6 Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .419 20-7 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .419 Technical Data 16 Pulse Accumulator 229 List of Figures MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... Multiplexed Expansion Bus Timing Diagram . . . . . . . . . . . . . 421 20-9 SPI Timing Diagram ( 423 20-10 SPI Timing Diagram ( 424 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor List of Figures List of Figures Technical Data 17 ...

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... List of Figures Technical Data 18 MC68HC912D60A — Rev. 3.1 List of Figures Freescale Semiconductor ...

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... PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . . 222 13-3 PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . . 222 14-1 Compare Result Output Action . . . . . . . . . . . . . . . . . . . . . . . . 238 14-2 Edge Detector Circuit Configuration . . . . . . . . . . . . . . . . . . . .238 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Title Device Ordering Information Development Tools Ordering Information M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . . 34 Summary of Indexed Operations ...

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... TTAGO Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392 19-6 TTAGO Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 19-7 Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 19-8 REGN Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 19-9 Breakpoint Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 19-10 Breakpoint Address Range Control . . . . . . . . . . . . . . . . . . . . 399 19-11 Breakpoint Read/Write Control . . . . . . . . . . . . . . . . . . . . . . . . 401 Technical Data 20 Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 List of Tables MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... Key Wake- .426 20-19 msCAN12 Wake-up Time from Sleep Mode 426 21-1 Suggested 8MHz Synthesis PLL Filter Elements 21-2 Suggested 8MHz Synthesis PLL Filter Elements MC68HC912D60A — Rev. 3.1 Freescale Semiconductor (Tracking Mode 431 (Acquisition Mode 432 List of Tables List of Tables ...

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... List of Tables Technical Data 22 MC68HC912D60A — Rev. 3.1 List of Tables Freescale Semiconductor ...

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... In addition to the I/O ports available in each module 80QFP) I/O port pins are available with Key-Wake-Up capability from STOP or WAIT mode. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Devices Covered in this Document Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ordering Information ...

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... Memory – 60K byte flash EEPROM, made of a 28K module and a 32K module with 8K bytes protected BOOT section in each module (MC68HC912D60A) – 1K byte EEPROM – 2K byte RAM General Description Section 12 start bit detector (112TQFP MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Analog-to-digital converters – 8-channels, 10-bit resolution in 112TQFP – 8-channels, 8-bit resolution in 80QFP 1M bit per second, CAN 2 software compatible module – Two receive and three transmit buffers – Flexible identifier filter programmable bit bit bit – ...

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... TQFP package or 80-pin QFP package – general-purpose I/O lines, plus input-only lines in 112TQFP general-purpose I/O lines, plus input-only lines in 80QFP 8MHz operation at 5V Development support – Single-wire background debug™ mode (BDM) – On-chip hardware breakpoints General Description MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... TQFP 112-Pin TQFP 80-Pin TQFP 112-Pin TQFP 80-Pin TQFP * Important: M temperature operation is available only for single chip modes MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Table 1-1. Device Ordering Information Ambient Temperature Package Range –40 to +85°C Single Tray –40 to +105°C 60 Pcs – ...

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... Third party tools: http://www.mcu.motsps.com/dev_tools/3rd/index.html Technical Data 28 Name Order Number Free from World Wide Web M68SDIL (3–5V), M68DIL12 (SDIL + MCUez + SDI SDBUG12) M68EVB912D60 (EVB only) EVB M68KIT912D60 (EVB + SDIL12) General Description MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... PE1 PE2 PE3 PE4 PE5 PE6 PE7 Multiplexed Address/Data Bus DDRA PORT A Wide bus Narrow bus Figure 1-1 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor VRH0 ATD0 VRL0 VDDAD VSSAD 2K byte RAM AN00 AN01 1K byte EEPROM AN02 AN03 AN04 AN05 CPU12 AN06 ...

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... PS3 PS4 PS5 PS6 PS7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 TxCAN PCAN1 RxCAN PCAN0 PG4 VDD ×2 VSS ×2 Power for internal circuitry VDDX ×2 VSSX ×2 PH4 Power for I/O drivers MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... Programming Model CPU12 registers are an integral part of the CPU and are not addressed as if they were memory locations. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Section 2. Central Processing Unit Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Indexed Addressing Modes ...

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... The program counter can be used in all indexed addressing modes except autoincrement/decrement. Technical Data Figure 2-1. Programming Model Central Processing Unit 0 8-BIT ACCUMULATORS A & 16-BIT DOUBLE ACCUMULATOR D 0 INDEX REGISTER X 0 INDEX REGISTER Y 0 STACK POINTER 0 PROGRAM COUNTER CONDITION CODE REGISTER MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... Addressing modes determine how the CPU accesses memory locations to be operated upon. The CPU12 includes all of the addressing modes of the M68HC11 CPU as well as several new forms of indexed addressing. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Bit data 8-bit and 16-bit signed and unsigned integers 16-bit unsigned fractions 16-bit addresses Table 2 summary of the available addressing modes ...

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... Operand is a 16-bit address pc Auto pre-increment accumulator offset from (16-bit offset in two extension bytes) Pointer to operand is found at... (16-bit offset in two extension bytes) Pointer to operand is found at... plus the value in D MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... A,r 111rr1aa 111rr111 [D,r] MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Specify which index register is used. Determine whether a value in an accumulator is used as an offset. Enable automatic pre- or post-increment or decrement Specify use of 5-bit, 9-bit, or 16-bit signed offsets. Table 2-2. Summary of Indexed Operations ...

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... To provide additional addressing flexibility, opcodes can also be followed by a postbyte or extension bytes. Postbytes implement certain forms of indexed addressing, transfers, exchanges, and loop primitives. Extension bytes contain additional program information such as addresses, offsets, and immediate data. Technical Data 36 Central Processing Unit MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... Technical Data — MC68HC912D60A 3.1 Contents 3.2 3.3 3.4 3.5 3.6 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Section 3. Pinout and Signal Descriptions MC68HC912D60A Pin Assignments in 112-pin QFP . . . . . . . . 38 MC68HC912D60A Pin Assignments in 80-pin QFP . . . . . . . . . 40 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Pinout and Signal Descriptions ...

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... Pinout and Signal Descriptions 84 PAD17/AN17 83 PAD07/AN07 PAD16/AN16 82 PAD06/AN06 81 80 PAD15/AN15 79 PAD05/AN05 78 PAD14/AN14 77 PAD04/AN04 PAD13/AN13 76 PAD03/AN03 75 74 PAD12/AN12 73 PAD02/AN02 72 PAD11/AN11 PAD01/AN01 71 PAD10/AN10 70 PAD00/AN00 RL0 67 V RH0 PA7/ADDR15/DATA15/DATA7 64 63 PA6/ADDR14/DATA14/DATA6 62 PA5/ADDR13/DATA13/DATA5 61 PA4/ADDR12/DATA12/DATA4 PA3/ADDR11/DATA11/DATA3 60 PA2/ADDR10/DATA10/DATA2 59 PA1/ADDR9/DATA9/DATA1 58 57 PA0/ADDR8/DATA8/DATA0 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... T L PIN 1 112 IDENT 1 VIEW 0.050 C θ C1 VIEW AB Figure 3-2. 112-pin TQFP Mechanical Dimensions (case no. 987) MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60A Pin Assignments in 112-pin QFP 0. TIPS VIEW AB θ 2 0.10 T 112X SEATING PLANE θ 0. GAGE PLANE (K) θ ...

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... Figure 3-3. Pin Assignments in 80-pin QFP for MC68HC912D60A Technical Data 40 MC68HC912D60A 80 QFP Pinout and Signal Descriptions 60 PAD07/AN07 59 PAD06/AN06 58 PAD05/AN05 57 PAD04/AN04 56 PAD03/AN03 55 PAD02/AN02 54 PAD01/AN01 53 PAD00/AN00 52 V RL0 51 V RH0 PA7/ADDR15/DATA15/DATA7 47 PA6/ADDR14/DATA14/DATA6 46 PA5/ADDR13/DATA13/DATA5 45 PA4/ADDR12/DATA12/DATA4 44 PA3/ADDR11/DATA11/DATA3 43 PA2/ADDR10/DATA10/DATA2 42 PA1/ADDR9/DATA9/DATA1 41 PA0/ADDR8/DATA8/DATA0 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

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... 0.20 M 0.05 A-B 0. -C- H SEATING PLANE G DATUM -H- PLANE W DETAIL C Figure 3-4. 80-pin QFP Mechanical Dimensions (case no. 841B) MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60A Pin Assignments in 80-pin QFP -B- DETAIL - A A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. ...

Page 42

... ATD converter 0. RL0 : reference voltage high and low for ATD converter 1. RL1 Pinout and Signal Descriptions and V . Because fast signal the ATD modules are not DD connected to V will not RH DD MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 43

... VDDPLL is tied to VDD but the PLL is switched off (PLLON bit cleared), then the XFC pin should be connected preferably to VDDPLL (i.e. ready for VCO minimum frequency). MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Appendix: CGM Practical Aspects MCU XFC Figure 3-5. PLL Loop FIlter Connections ...

Page 44

... Reference voltages for the analog-to-digital converter 0. 68 Provides operating voltage and ground for the Phased-Locked 43 Loop. This allows the supply voltage to the PLL bypassed independently. Section 12. Oscillator for details of crystal connections. Pinout and Signal Descriptions Description MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 45

... MCU to interface to slow external memory. ECLK can be stretched for such accesses. 3.5.3 Reset (RESET) An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known start-up state. It also acts as an open-drain MC68HC912D60A — Rev. 3.1 Freescale Semiconductor EXTAL MCU XTAL NC Figure 3-6. External Oscillator Connections ...

Page 46

... COP timeout is true, processing begins by fetching the COP Technical Data 46 Power-on-reset (POR) COP watchdog enabled and watchdog timer times out Clock monitor enabled and Clock monitor detects slow or stopped clock User applies a low level to the reset pin Pinout and Signal Descriptions MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 47

... If the interrupt line is held low, the MCU will recognize another interrupt as soon as the interrupt mask bit in the MCU is cleared (normally upon return from an interrupt). MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Pinout and Signal Descriptions Pinout and Signal Descriptions Signal Descriptions ...

Page 48

... DATA[7:0], depending on the bus cycle. The state of the address pin should be latched at the rising edge allow for maximum address setup time at external devices, a transparent latch should be used. Technical Data 48 Development Support. Pinout and Signal Descriptions MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 49

... DBE is controlled by the NDBE bit in the PEAR register.DBE is enabled out of reset in expanded modes. This pin has an active pull-up during and after reset in single chip modes. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Development Support. Pinout and Signal Descriptions Pinout and Signal Descriptions ...

Page 50

... Crystal driver and external clock input pins. An active low bidirectional control signal, RESET acts as an input to initialize the MCU to a known start-up state, and an output when COP or clock monitor causes a reset. Pinout and Signal Descriptions MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 51

... SCK 69 95 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Description External bus pins share function with general-purpose I/O ports A and B. In single chip modes, the pins can be used for I/O. In expanded modes, the pins are used for the external buses. Data bus control and, in expanded mode, enables the drive control of external buses during external reads ...

Page 52

... Key wake-up and general purpose I/O; can cause an interrupt when an input transitions from high to low. On 80-pin QFP all 8 I/O should be initialised. Defines if I/O port resistive load is a pull- pull-down, when enabled. Pinout and Signal Descriptions MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 53

... Setting a bit in DDRB makes the corresponding bit in port B an output; clearing a bit in DDRB makes the corresponding bit in port B an input. The default reset state of DDRB is all zeros. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Pinout and Signal Descriptions Pinout and Signal Descriptions Port Signals ...

Page 54

... Setting the RDPE bit in register RDRIV causes all port E outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Input/Output. Technical Data 54 Pinout and Signal Descriptions Bus Control and Bus Control and MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 55

... I/O pin. Refer to Register DDRH determines pin direction of Port H when used for general-purpose I/O. When DDRH bits are set, the corresponding pin is MC68HC912D60A — Rev. 3.1 Freescale Semiconductor I/O Ports with Key Wake-up. I/O Ports with Key Wake-up. ...

Page 56

... Input to the analog-to-digital subsystem and general-purpose input. When analog-to-digital functions are not enabled, the port has eight general-purpose input pins, PAD1[7:0]. The ADPU bit in the ATD1CTL2 register enables the A/D function. Technical Data 56 Pinout and Signal Descriptions Bus Control and MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 57

... Setting the RDPP bit in the PWCTL register configures all port P outputs to have reduced drive levels. Levels are at normal drive capability after reset. The PWCTL register can be read or written anytime after reset. Refer to MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Analog-to-Digital Converter. Analog-to-Digital Converter. ...

Page 58

... When the PUPT bit in the TMSK2 register is set, all input pins are pulled up internally by an active pull-up device. Pull-ups are disabled after reset. Technical Data 58 Multiple Serial Pinout and Signal Descriptions Interface. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 59

... PT[7:0] 7–4 7– 80-pin QFP package only TxCAN and RxCAN are available. PortCAN[2:7] pins should either be defined as outputs or have their pull-ups enabled. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Enhanced Capture Timer. . MC68HC912D60A Port Description Summary Data Direction Register (Address) ...

Page 60

... Bit Name State RDPA Full drive RDPB Full drive RDPE Full drive RDPE Full drive RDPG Full drive RDPH Full drive Full drive RDPS0 Full drive RDPS1 Full drive RDPS2 Full drive TDRB Full drive MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 61

... The register block occupies the first 512 bytes of the 2K byte block. Default addressing (after reset) is indicated in Table Resource MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Register Block 4-1. For additional information refer to Mapping. Registers Section 4. Registers Operating Modes and ...

Page 62

... INITRG 0 0 EEON INITEE MISC RTR1 RTR0 RTICTL RTIFLG CR2 CR1 CR0 COPCTL 2 1 Bit 0 COPRST Reserved Reserved Reserved Reserved Reserved Reserved INTCR PSEL1 0 HPRIO 0 0 BRKCT0 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor (1) (1) (1) (1) (3) (3) (3) (3) (2) (2) (3) (3) (3) (3) (3) (3) ...

Page 63

... Bit 6 $0044 Bit 7 6 $0045 Bit 7 6 $0046 Bit 7 6 $0047 Bit 7 6 $0048 Bit 7 6 $0049 Bit 7 6 $004A Bit 7 6 Table 4-1. MC68HC912D60A Register Map (Sheet MC68HC912D60A — Rev. 3.1 Freescale Semiconductor BKMBH BKMBL BK1RWE PG5 PG4 PG3 ...

Page 64

... Reserved ATD0CTL0 ATD0CTL1 R ASCIE ASCIF ATD0CTL2 FIFO FRZ1 FRZ0 ATD0CTL3 PRS1 PRS0 ATD0CTL4 ATD0CTL5 CC2 CC1 CC0 ATD0STAT0 CCF1 CCF0 ATD0STAT1 SAR3 SAR2 ATD0TESTH TST1 TST0 ATD0TESTL Reserved PAD01 PAD00 PORTAD0 10 9 Bit 8 ADR00H ADR00L MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 65

... EDG3A $008C C7I C6I $008D TOI 0 $008E C7F C6F $008F TOF 0 $0090 Bit 15 14 $0091 Bit 7 6 $0092 Bit 15 14 $0093 Bit 7 6 $0094 Bit 15 14 $0095 Bit 7 6 Table 4-1. MC68HC912D60A Register Map (Sheet MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 66

... TIMTST PT1 PT0 PORTT DDT1 DDT0 DDRT 0 PBOVI 0 PBCTL 0 PBOVF 0 PBFLG 2 1 Bit 0 PA3H 2 1 Bit 0 PA2H 2 1 Bit 0 PA1H 2 1 Bit 0 PA0H 10 9 Bit 8 MCCNTH 2 1 Bit 0 MCCNTL 10 9 Bit 8 TC0H 2 1 Bit 0 TC0H MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 67

... Bit 7 6 $00D6 PS7 PS6 $00D7 DDS7 DDS6 $00D8 0 0 $00D9 0 RDPS2 $00DA– $00DF $00E0– $00ED $00EE 0 0 Table 4-1. MC68HC912D60A Register Map (Sheet MC68HC912D60A — Rev. 3.1 Freescale Semiconductor BRLD SBR12 SBR11 SBR5 SBR4 SBR3 RSRC ...

Page 68

... AC1 AC0 CIDAR0 AC2 AC1 AC0 CIDAR1 AC2 AC1 AC0 CIDAR2 AC2 AC1 AC0 CIDAR3 AM2 AM1 AM0 CIDMR0 AM2 AM1 AM0 CIDMR1 AM2 AM1 AM0 CIDMR2 AM2 AM1 AM0 CIDMR3 AC2 AC1 AC0 CIDAR4 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 69

... CCF7 CCF6 $01E8 SAR9 SAR8 $01E9 SAR1 SAR0 $01EA– 01EE $01EF PAD17 PAD16 Table 4-1. MC68HC912D60A Register Map (Sheet MC68HC912D60A — Rev. 3.1 Freescale Semiconductor AC5 AC4 AC3 AC5 AC4 AC3 AC5 AC4 AC3 AM5 AM4 AM3 AM5 AM4 ...

Page 70

... Registers 1 Bit 0 Name 9 Bit 8 ADR10H 0 0 ADR10L 9 Bit 8 ADR11H 0 0 ADR11L 9 Bit 8 ADR12H 0 0 ADR12L 9 Bit 8 ADR13H 0 0 ADR13L 9 Bit 8 ADR14H 0 0 ADR14L 9 Bit 8 ADR15H 0 0 ADR15L 9 Bit 8 ADR16H 0 0 ADR16L 9 Bit 8 ADR17H 0 0 ADR17L MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 71

... BKGD, MODB, and MODA pins during reset. The SMODN, MODB, and MODA bits in the MODE register show current operating mode and provide limited mode switching during operation. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Internal Resource Mapping .77 Memory Maps ...

Page 72

... Operating Modes and Resource Mapping Port A Port B G.P. I/O G.P. I/O ADDR/DATA ADDR — — ADDR/DATA ADDR/DATA G.P. I/O G.P. I/O ADDR/DATA ADDR ADDR/DATA ADDR/DATA ADDR/DATA ADDR/DATA MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 73

... I.C. tester, can control the on-chip peripherals. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Normal Single-Chip Mode — There are no external address and data buses in this mode. The MCU operates as a stand- alone device and all program and data resources are on-chip. ...

Page 74

... Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both modes. Operating Modes and Resource Mapping MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 75

... SMODN is Read anytime. May only be written in special modes (SMODN = 0). The first write is ignored; MODB, MODA may be written once in Normal modes (SMODN = 1). Write anytime in special modes (first write is ignored) – special peripheral and reserved modes cannot be selected. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MODA ESTR ...

Page 76

... External bus and registers continue functioning during wait mode External bus is shut down during wait mode. Normal modes: write anytime; Special modes: write never. Read anytime. Technical Data 76 Operating Modes and Resource Mapping MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 77

... In expanded modes, all address space not used by internal resources is by default external memory. The MC68HC912D60A contains 60K bytes of Flash EEPROM nonvolatile memory which can be used to store program code or static MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Operating Modes and Resource Mapping Operating Modes and Resource Mapping Internal Resource Mapping Technical Data ...

Page 78

... Normal modes: write once; special modes: write anytime. Read anytime. Technical Data 78 Table 5-2. Mapping Precedence Precedence 1 BDM ROM (if active On-Chip Flash EEPROM (MC68HC912D60A REG13 REG12 REG11 Operating Modes and Resource Mapping Resource Register Space RAM EEPROM External Memory 2 1 Bit MMSWAI MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $0011 ...

Page 79

... INITRM — Initialization of Internal RAM Position Register RAM[15:11] — Internal RAM map position These bits specify the upper five bits of the 16-bit RAM address. Normal modes: write once; special modes: write anytime. Read anytime. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor RAM13 RAM12 ...

Page 80

... This bit is forced to one in single-chip modes. Read or write anytime Removes the EEPROM from the map Places the on-chip EEPROM in the memory map at the address selected by EE[15:12]. Technical Data EE13 EE12 Operating Modes and Resource Mapping 2 1 Bit EEON $0012 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 81

... Makes the Register-Following MAP space act the same bit only external data bus (data only goes through port A externally). The Register-Following space is mapped from $0200 to $03FF after reset, which is next to the register map. If the registers are moved this space follows. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor RFSTR1 RFSTR0 ...

Page 82

... Corresponding Flash EEPROM array enabled in the memory map. Technical Data 82 Table 5-3. RFSTR Stretch Bit Definition RFSTR1 RFSTR0 Table 5-4. EXSTR Stretch Bit Definition EXSTR1 EXSTR0 Operating Modes and Resource Mapping Number of E Clocks Stretched Number of E Clocks Stretched MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 83

... EXT $FF00 VECTORS VECTORS $FFFF NORMAL EXPANDED SINGLE CHIP Figure 5-1 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor VECTORS SPECIAL SINGLE CHIP . MC68HC912D60A Memory Map Operating Modes and Resource Mapping Operating Modes and Resource Mapping Memory Maps $0000 REGISTERS (MAPPABLE TO ANY 2K SPACE) ...

Page 84

... Operating Modes and Resource Mapping Technical Data 84 Operating Modes and Resource Mapping MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 85

... LSTRB = because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these cases the data for the address MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Section 6. Bus Control and Input/Output Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Detecting Access Type from External Signals . . . . . . . . . . . . . 85 Registers ...

Page 86

... Bus Control and Input/Output Type of Access MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 87

... DDRA — Port A Data Direction Register This register determines the primary direction for each port A pin when functioning as a general-purpose I/O port. DDRA is not in the on-chip map in expanded and peripheral modes. Read and write anytime. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor PA5 ...

Page 88

... Associated pin is a high-impedance input 1 = Associated pin is an output Bus Control and Input/Output 2 1 Bit 0 PB2 PB1 PB0 — — — ADDR2/ ADDR1/ ADDR0/ DATA2 DATA1 DATA0 ADDR2 ADDR1 ADDR0 2 1 Bit 0 DDB2 DDB1 DDB0 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $0001 $0003 ...

Page 89

... Read and write anytime. Bit 7 6 DDE7 DDE6 RESET DDRE — Port E Data Direction Register This register determines the primary direction for each port E pin configured as general-purpose I/O. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor PE5 PE4 PE3 — — — LSTRB or MODA or ...

Page 90

... Technical Data Associated pin is a high-impedance input 1 = Associated pin is an output PIPOE NECLK LSTRE Bus Control and Input/Output 2 1 BIT 0 RDWE CALE DBENE Normal Expanded Special Expanded Peripheral Normal single chip Special single chip MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $000A ...

Page 91

... CGMTE — Clock Generator Module Testing Enable Normal: write never; Special: write anytime EXCEPT the first. Read anytime. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor 0 = PE7 is used for DBE, external control of data enable on memories, or inverted ECLK PE7 is the CAL function if CALE bit is set in PEAR register or general-purpose I/O ...

Page 92

... ESTR = 0 in addition to NECLK = PE4 is a general-purpose I/O pin PE3 is a general-purpose I/O pin PE3 is configured as the LSTRB bus-control output, provided the MCU is not in single chip or normal expanded narrow modes. Bus Control and Input/Output MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 93

... PE7 is defaulted to the CAL function if the CALE bit is set in the PEAR register I/O otherwise. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor 0 = PE2 is a general-purpose I/O pin PE2 is configured as the R/W pin. In single chip modes, RDWE has no effect and PE2 is a general-purpose I/O pin. ...

Page 94

... Enable pull-up devices for port E input pins PE7 and PE[3:0 Port B pull-ups are disabled Enable pull-up devices for all port B input pins Port A pull-ups are disabled Enable pull-up devices for all port A input pins. Bus Control and Input/Output 2 1 Bit 0 0 PUPB PUPA $000C MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 95

... Normal: write once; Special: write anytime EXCEPT the first time. Read anytime. RDPH — Reduced Drive of Port H RDPG — Reduced Drive of Port G RDPE — Reduced Drive of Port E RDPB — Reduced Drive of Port B RDPA — Reduced Drive of Port A MC68HC912D60A — Rev. 3.1 Freescale Semiconductor RDPG 0 RDPE 0 ...

Page 96

... Bus Control and Input/Output Technical Data 96 Bus Control and Input/Output MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 97

... The Flash EEPROM is ideal for program storage for single-chip applications allowing for field reprogramming. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Section 7. Flash Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Overview .98 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . . 98 Flash EEPROM Arrays ...

Page 98

... Flash EEPROM array is from $1000 to $7FFF. In expanded modes, the Flash EEPROM arrays are turned off. The Flash EEPROM can be mapped to an alternate address range. See Operating Modes and Resource Technical Data 98 FPOPEN). Mapping. Flash Memory 7.11 Flash MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 99

... BOOTP — Boot Protect FEE32CTL/FEE28CTL — Flash EEPROM Control Register Bit RESET This register controls the programming and erasure of the Flash EEPROM. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor normal modes the LOCK bit can only be written once after reset Enable write to FEEMCR register ...

Page 100

... Halt Flash EEPROM clock when the part is in wait mode Disables high voltage to array and charge pump off 1 = Enables high voltage to array and charge pump Erase operation is not selected Erase operation selected Program operation is not selected Program operation selected. Flash Memory MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 101

... Programming is restricted to aligned word i.e. data writes to select rows/blocks for programming/erase should be to even adresses and writes to any row for programming should be to aligned words. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Programming the Flash EEPROM FPGM Flash Memory Flash Memory maximum (40µ ...

Page 102

... If BOOTP is asserted, an attempt to program an address in the boot block will be ignored. (min. 30µs – max. 40µs). FPGM programmed. (min. 5µs). NVH (min 1µs), the memory can be accessed in read RCV mode again. Flash Memory MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 103

... The boot block will be erased only if the control bit BOOTP is negated. (min. 10µs). NVS (8ms). ERAS (min. 100µs). NVHL (min 1µs), the memory can be accessed in read RCV mode again. Flash Memory MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 104

... FPOPEN bit in the EEMCR register will always be ’0’ in normal modes. The flash array can no longer be modified in normal modes. Technical Data 104 0 = The whole Flash array (32-Kbyte and 28-Kbyte) is protected The whole Flash array (32-Kbyte and 28-Kbyte) is enabled for program or erase Flash Memory MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 105

... The erased state is $FF. The EEPROM module has hardware interlocks which protect stored data from corruption by accidentally enabling the MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Section 8. EEPROM Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 EEPROM Selective Write More Zeros . . . . . . . . . . . . . . . . . . 106 EEPROM Programmer’ ...

Page 106

... When this technique is utilized, a program / erase cycle is defined as multiple writes (up to eight unique location followed by a single erase sequence. Technical Data 106 supply with an internal charge pump. DD EEPROM Memory Result = binary 1111:1110 Result = binary 1111:1100 Result = binary 1111:1000 Result = binary 1111:0000 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 107

... At the next reset the SHADOW word data is loaded into the EEMCR, EEDIVH and EEDIVL registers. The SHADOW word can be protected from being programmed or erased by setting the SHPROT bit of EEPROT register. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Mapping. EEPROM Memory EEPROM Memory EEPROM Programmer’s Model ...

Page 108

... Technical Data 108 VCOMIN EEDIV5 EEDIV4 EEDIV3 EEDIV2 (1) (1) (1) — — — EEPROM Memory using a predefined divider $00EE 2 1 Bit 0 0 EEDIV9 EEDIV8 (1) (1) 0 — — $00EF 2 1 Bit 0 EEDIV1 EEDIV0 (1) (1) (1) — — — MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 109

... EEPROM with oscillator frequencies less than 250 Khz. The EEDIV value is determined by the following formula: NOTE: INT[A] denotes the round down integer value of A. Program/erase cycles will not be activated when EEDIV = 0. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor [ EEDIV = INT EXTALi Table 8-1. EEDIV Selection Osc Freq ...

Page 110

... Reserved FPOPEN — — The BDM lockout is enabled The BDM lockout is disabled The SHADOW word is enabled and accessible at address $0FC0-$0FC1 Regular EEPROM array at address $0FC0-$0FC1. EEPROM Memory 2 1 Bit 0 EESWAI PROTLCK DMY MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $00F0 ...

Page 111

... DMY— Dummy bit Read and write anytime. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor 0 = The whole Flash array (32-Kbyte and 28-Kbyte) is protected The whole Flash array (32-Kbyte and 28-Kbyte) is enable for program or erase The module is not affected during WAIT mode ...

Page 112

... Block Protected BPROT4 $0C00 to $0DFF BPROT3 $0E00 to $0EFF BPROT2 $0F00 to $0F7F BPROT1 $0F80 to $0FBF BPROT0 $0FC0 to $0FFF EEPROM Memory 2 1 Bit 0 BPROT2 BPROT1 BPROT0 Block Size 512 Bytes 256 Bytes 128 Bytes 64 Bytes 64 Bytes MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $00F1 ...

Page 113

... BYTE and ROW have no effect when ERASE = 0 If BYTE = 1 only the location specified by the address written to the programming latches will be erased. The operation will be a byte or an aligned word erase depending on the size of written data. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor AUTO ...

Page 114

... Technical Data 114 0 = EEPROM configuration for programming EEPROM configuration for erasure EEPROM set up for normal reads EEPROM address and data bus latches set up for programming or erasing Disables program/erase voltage to EEPROM Applies program/erase voltage to EEPROM. EEPROM Memory MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 115

... EEMCR, EEDIVH and EEDIVL after reset. shows the mapping of each bit from shadow word to the registers 1. Reserved for testing. Must be set to one in user application. 2. Reserved. Must be set to one in user application for future compatibility. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor or erase, t PROG Table 8-4. Shadow word mapping ...

Page 116

... Program bits 1 and 0 of the high byte of the SHADOW word and Technical Data 116 based on the oscillator frequency as per Table17. EEPROT register. visible at $0FC0-$0FC1. bits the low byte of the SHADOW word like a regular EEPROM Memory MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 117

... Protect the SHADOW word by setting SHPROT bit in EEPROT MC68HC912D60A — Rev. 3.1 Freescale Semiconductor EEPROM location at address $0FC0 and $0FC1. Do not program other bits of the high byte of the SHADOW word (location $0FC0); otherwise some regular EEPROM array locations will not be visible. At the next reset, the SHADOW values are loaded into the EEDIVH and EEDIVL registers ...

Page 118

... EEPROM Memory Technical Data 118 EEPROM Memory MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 119

... Exception Priority A hardware priority hierarchy determines which reset or interrupt is serviced first when simultaneous requests are made. Six sources are not MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Section 9. Resets and Interrupts Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Interrupt Control and Priority Registers ...

Page 120

... I bit in the CCR any associated local bits. Interrupt vectors are not affected by priority assignment. HPRIO can only be written while the I bit is set (interrupts inhibited). sources and vectors in default order of priority. Technical Data 120 Resets and Interrupts Table 9-1 lists interrupt MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 121

... These interrupt flags should be cleared during an interrupt service routine or when interrupts are masked by the I bit. By doing this, the MCU will never get an unknown interrupt source and take the trap vector. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Resets and Interrupts Resets and Interrupts Latching of Interrupts ...

Page 122

... TMSK1 (C6I) $E2 TMSK1 (C7I) $E0 TMSK2 (TOI) $DE PACTL (PAOVI) $DC PACTL (PAI) $DA SP0CR1 (SPIE) $D8 SC0CR2 $D6 SC1CR2 $D4 $D2 CRIER (WUPIE) $D0 KWIEG[6:0] and $CE KWIEH[7:0] MCCTL (MCZI) $CC PBCTL (PBOVI) $CA CRIER (RWRNIE, TWRNIE, $C8 BOFFIE, OVRIE) CRIER (RXFIE) $C6 $C4 $C2 $80–$C0 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 123

... DLY — Enable Oscillator Start-up Delay on Exit from STOP The delay time of about 4096 cycles is based on the X clock rate chosen. DLY can be read anytime and written once in normal modes. In special modes, DLY can be read and written anytime. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor DLY 0 ...

Page 124

... It is important to use an external low voltage reset circuit (for example: MC34064 or MC33464) to prevent power transitions or corruption of RAM or EEPROM. Technical Data 124 PSEL5 PSEL4 PSEL3 PSEL2 causes a power-on reset (POR). An external DD Resets and Interrupts 2 1 Bit 0 PSEL1 $001F MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 125

... A premature write will also reset the part. 9.6.4 Clock Monitor Reset If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Resets and Interrupts Resets and Interrupts Resets Technical Data ...

Page 126

... However, the interrupt mask bits in the CPU12 CCR are set to mask X- and I-related interrupt requests. 9.7.4 Parallel I/O If the MCU comes out of reset in a single-chip mode, all ports are configured as general-purpose high-impedance inputs. Technical Data 126 Resets and Interrupts MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 127

... I bit in the CCR is cleared. When an interrupt service request is recognized, the CPU responds at the completion of the instruction being executed. Interrupt latency varies according to the number of cycles MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Resets and Interrupts Resets and Interrupts Register Stacking Technical Data ...

Page 128

... Technical Data 128 Table 9-2. Stacking Order on Entry to Interrupts Memory Location SP – – – – – 9 Resets and Interrupts Table 9-2. CPU Registers RTN : RTN CCR MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 129

... KWIEG or KWIEH bit are both set. All 15 bits/pins share the same interrupt vector. Key wake-ups can be used with the pins configured as inputs or outputs. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Section 10. I/O Ports with Key Wake-up Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . . 130 Key Wake-Up Input Filter ...

Page 130

... PH3 — — — KWH5 KWH4 KWH3 KWH2 I/O Ports with Key Wake-up Mapping Bit 0 PG2 PG1 PG0 — — — KWG1 KWG0 2 1 Bit 0 PH2 PH1 PH0 — — — KWH1 KWH0 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $0028 $0029 ...

Page 131

... DDH7 DDH6 RESET DDRH — Port H Data Direction Register Data direction register H is associated with port H and designates each pin as an input or output. Read and write anytime. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor DDG5 DDG4 DDG3 Associated pin is an input 1 = Associated pin is an output ...

Page 132

... Interrupt for the associated bit is enabled KWIEH5 KWIEH4 KWIEH3 Interrupt for the associated bit is disabled 1 = Interrupt for the associated bit is enabled I/O Ports with Key Wake- Bit 0 KWIEG2 KWIEG1 KWIEG0 Bit 0 KWIEH2 KWIEH1 KWIEH0 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $002C 2 C $002D ...

Page 133

... Read and write anytime Bit 7 always reads zero. KWIFG6 — Key Wake-up Port G Flag 6 Depending on WI2CE bit in KWIEG register, KWIFG6 flags either falling edge or I2C Start condition. KWIFG[5:0] — Key Wake-up Port G Flags MC68HC912D60A — Rev. 3.1 Freescale Semiconductor KWIFG5 KWIFG4 KWIFG3 ...

Page 134

... Falling edge on the associated bit has not occurred 1 = Falling edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set) in order to be considered as a single pulse by the filter. If KWSP I/O Ports with Key Wake- Bit 0 KWIFH2 KWIFH1 KWIFH0 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $002F ...

Page 135

... Glitch, filtered out, no STOP wake-up Valid STOP Wake-Up pulse t KWSTP Minimum time interval between pulses to be recognized as single pulses Figure 10-1. STOP Key Wake-up Filter (falling edge trigger) timing MC68HC912D60A — Rev. 3.1 Freescale Semiconductor KWSP min. t max. KWSTP t KWSP ...

Page 136

... I/O Ports with Key Wake-up Technical Data 136 I/O Ports with Key Wake-up MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 137

... CPU and on-chip peripherals. A clock monitor circuit, a computer operating properly (COP) watchdog circuit, and a periodic interrupt circuit are also incorporated into the MC68HC912D60A. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Section 11. Clock Functions Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Clock Sources 138 Phase-Locked Loop (PLL 139 Acquisition and Tracking Modes ...

Page 138

... COP clocks. The slow clock bus frequencies divide the crystal frequency in a programmable range 252, with steps of 4. Figure 11-1 Divider Chains Technical Data 138 shows some of the timing relationships. See the section for further details. Clock Functions Clock MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 139

... Refer to Signal MC68HC912D60A — Rev. 3.1 Freescale Semiconductor for an overview of system clocks. Descriptions. Clock Functions Clock Functions Phase-Locked Loop (PLL) ...

Page 140

... Technical Data 140 LOCK REFDV <2:0> DETECTOR REFERENCE PROGRAMMABLE REFCLK DIVIDER PDET PHASE DIVCLK DETECTOR LOOP PROGRAMMABLE LOOP DIVIDER FILTER SYN <5:0> XCLK XFC Clock Functions LOCK UP CPUMP VCO DOWN VDDPLL XFC × 2 PAD PLLCLK description. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 141

... PLL start-up, usually periodic intervals. In either case, when the LOCK bit is set, the PLLCLK clock is safe to use as the source MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency ...

Page 142

... PLL control register. This is to avoid switching to tracking mode too early while the XFC voltage level is still too far away from its quiescent value corresponding to the target frequency. This operation would be very detrimental to the stabilization time. Clock Functions Chains. If the VCO is selected as MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 143

... PLL or operation with VDDPLL at VSS level. With limp home mode enabled (NOLHM bit cleared) and the clock monitor enabled (CME or FCME bits set loss of clock, the PLL MC68HC912D60A — Rev. 3.1 Freescale Semiconductor During normal clock operation. At Power-On Reset. In the STOP exit sequence ...

Page 144

... BCSP and MCS signals are restored to their Technical Data 144 ) and ECLK is also equal to f VCOMIN --> 4096 0 --> 4096 PLLCLK (Limp-Home) Clock Functions is provided as the system , VCOMIN MSCAN clock . VCOMIN Restore BCSP Restore PLLCLK or EXTALi MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 145

... With the VDDPLL supply voltage at VDD level, any reset sets the Clock Monitor Enable bit (CME) and the PLLON bit and clears the NOLHM bit. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Limp-Home and Fast STOP Recovery modes Figure 11-3 Clock Functions ...

Page 146

... XCLK) BCSP Internal reset SYSCLK PLLCLK (L.H.) SYSCLK (Slow EXTALi) Figure 11-4. No Clock at Power-On Reset Technical Data 146 (Slow EXTALi) 0 --> 4096 EXTALi PLLCLK (Software check of Limp-Home Flag) Clock Functions Reset: BCSP = 0 EXTALi MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 147

... EXTALi. The internal reset period and MCU operation will execute only on EXTALi clock. NOTE: The external clock signal must stabilise within the initial 4096 reset counter cycles. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Limp-Home and Fast STOP Recovery modes Clock Functions Clock Functions . VCOMIN ...

Page 148

... DLY=0 is only recommended when there is a good signal available at the EXTAL pin (e.g. an external square wave source). STOP mode is exited with an external reset, an external interrupt from IRQ or XIRQ, a Key Wake-Up interrupt from port J or port MSCAN Wake-Up interrupt. Technical Data 148 MC68HC912D60A — Rev. 3.1 Clock Functions Freescale Semiconductor ...

Page 149

... XCLK cycles. NOTE: The external clock signal should stabilise within the 4096 reset counter cycles. Use of DLY=0 is not recommended due to this requirement. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor 0 --> 4096 Restore BCSP PLLCLK (L.H.) Restore PLLCLK or EXTALi ...

Page 150

... LHIE bit, the limp-home mode interrupt is requested. CAUTION: The clock monitor circuit can be misled by EXTALi clock into reporting a good signal before it has fully stabilised. Under these conditions, Technical Data 150 MC68HC912D60A — Rev. 3.1 Clock Functions ), following a VCOMIN Freescale Semiconductor ...

Page 151

... CAUTION: This mode is not recommended since the risk of the clock monitor detecting incorrect clocks is high. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Limp-Home and Fast STOP Recovery modes Clock Functions Clock Functions Technical Data 151 ...

Page 152

... IRQ or XIRQ, a Key Wake-Up interrupt from port J or port MSCAN Wake-Up interrupt. The effect of the DLY bit is the same as noted above in Fast STOP Technical Data 152 Recovery. Clock Functions STOP Exit and MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 153

... CPU to function incorrectly with a resultant risk of code runaway. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Limp-Home and Fast STOP Recovery modes ) with both the LHOME flag set and the LHIF limp- ...

Page 154

... Technical Data 154 and Table 11-2 summarise the exit conditions from STOP =V ). The RESET wakeup pulse must be longer than the DDPLL DD Clock Functions MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 155

... Home mode, clock monitor disabled, with Delay Pseudo-STOP exit without Limp Home mode, clock monitor disabled, without Delay MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Limp-Home and Fast STOP Recovery modes Conditions NOLHM=1 Oscillator must be stable within 4096 XCLK cycles. XCLK CME=0 can be modified by SLOW divider register ...

Page 156

... CGTFLG — Clock Generator Test Register Always reads zero, except in test modes. Technical Data 156 SYN5 SYN4 SYN3 REFDV2 TSTOUT5 TSTOUT4 TSTOUT3 TSTOUT2 Clock Functions 2 1 Bit 0 SYN2 SYN1 SYN0 Bit 0 REFDV1 REFDV0 Bit 0 TSTOUT1 TSTOUT0 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $0038 $0039 $003A ...

Page 157

... Write has no effect on LOCK bit. This bit is cleared in limp-home mode as the lock detector cannot operate without the reference frequency. LHIF — Limp-Home Interrupt Flag To clear the flag, write one to this bit in PLLFLG. LHOME — Limp-Home Mode Status For Limp-Home mode, see MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 158

... Turns on the phase lock loop circuit. If AUTO is set, the PLL will lock automatically Automatic Mode Control is disabled and the PLL is under software control, using ACQ bit Automatic Mode Control is enabled. ACQ bit is read only. Specifications. Clock Functions 2 1 Bit 0 PSTP LHIE NOLHM 0 0 (2) — MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $003C ...

Page 159

... Read anytime; Normal modes: write once; Special modes: write anytime. Forced to 1 when VDDPLL is at VSS level. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor 0 = PLL VCO is not within the desired tolerance of the target frequency. The loop filter is in high bandwidth, acquisition mode. ...

Page 160

... SYSCLK is derived from the crystal clock or from SLWCLK SYSCLK source is the PLL SYSCLK is derived from the crystal clock EXTALi SYSCLK source is the Slow clock SLWCLK clock is the same as PCLK clock is derived from Slow clock SLWCLK. Clock Functions 2 1 Bit 0 MCS MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $003D ...

Page 161

... When SLOW = 0, the divider is bypassed. The generation and M clocks further divides SLWCLK by 2. Hence, the final ratio of Bus to EXTALi Frequency is programmable 12, 16, 20, ..., 252, by steps of 4. SLWCLK is a 50% duty cycle signal. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor SLDV5 SLDV4 ...

Page 162

... MC68HC912D60A SYSCLK is slower than EXTALi (BCSS=1, BCSP=0, SLOW>0), BCLK becomes ECLK. Technical Data 162 11-6: (1) = EXTALi / 2 11-6, Figure 11-7, Figure 11-8, and Clock Functions SLOW = 1,2,..63 SLOW = 0 Figure 11-9 summarize the MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 163

... Bus clock select bits BCSP and BCSS in the clock select register (CLKSEL) determine which clock drives SYSCLK for the main system including the CPU and buses. BCSS has no effect if BCSP is set. During MC68HC912D60A — Rev. 3.1 Freescale Semiconductor BCSP BCSS 1:x SYSCLK ÷ ...

Page 164

... RECEIVE BAUD RATE (16x) ÷ 16 ÷ 2 1:1:1 SCI1 TRANSMIT BAUD RATE (1x) Clock Functions 0:0:0 REGISTER: COPCTL BITS: CR2, CR1, CR0 0:0:1 ÷ 0:1:0 4 ÷ 0:1:1 4 ÷ 4 1:0:0 ÷ 4 1:0:1 ÷ 2 1:1:0 ÷ 2 1:1:1 TO RTI TO COP MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 165

... PORT T7 PAEN MC68HC912D60A — Rev. 3.1 Freescale Semiconductor REGISTER: MCCTL BITS: MCPR1, MCPR0 MCEN 0:0 0:1 ÷ 4 ÷ 1:0 2 1:1 ÷ 2 Prescaled MCLK PULSE ACC LOW BYTE PULSE ACC PACLK GATE ...

Page 166

... ECLKs while output is high impedance, Drive out 1 E cycle pulse high, high imped- ance output again Transmit 0: Detect falling edge, Drive out low, count 9 ECLKs, Drive out 1 E cycle pulse high, high impedance output MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 167

... EXTALi clock. Clock monitor time-outs are shown in EXTALi clock period with an ideal 50% duty cycle is twice this time-out value. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Table Table 11-3. Clock Monitor Time-Outs Supply 5 V +/– 10% Clock Functions ...

Page 168

... This is useful for emulation Divider chain functions normally Divider chain is bypassed, allows faster testing (the divider chain is normally XCLK divided by 2 becomes XCLK divided by 4). Clock Functions 2 1 Bit 0 RTR2 RTR1 RTR0 when bypassed MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $0014 ...

Page 169

... RTIFLG — Real Time Interrupt Flag Register RTIF — Real Time Interrupt Flag This bit is cleared automatically by a write to this register with this bit set. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Table 11-4. Real Time Interrupt Rates Time-Out Period Time-Out Period X = 125 KHz ...

Page 170

... Clock monitor follows the state of the CME bit Slow or stopped clocks will cause a clock reset sequence or limp-home mode. Limp-Home and Fast STOP Recovery Clock Functions 2 1 Bit 0 CR2 CR1 CR0 Normal Special modes. modes. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor $0016 Limp- ...

Page 171

... RTI section is not cleared when the COP counter is cleared. This means the effective window is reduced by this uncertainty. 5 available COP rates. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor 0 = Normal operation clock monitor failure reset or a COP failure reset is forced depending on the state of CME and if COP is enabled. CME ...

Page 172

... Regardless of other control bit states, COP and clock monitor will not generate a system reset. Clock Functions Window COP enabled: Effective Window end (1) Window OFF OFF OFF 0.768 3.840 ms 18.8 % 16.128 ms 23.4 % 64.512 ms 23.4 % 261.120 ms 24.6 % 523.264 ms 24.8 % 1.047552 s 24.9 % MC68HC912D60A — Rev. 3.1 Freescale Semiconductor (2) (3) ...

Page 173

... Other instructions may be executed between these writes but both must be completed in the correct order prior to time-out to avoid a watchdog reset. Writing anything other than $55 or $AA causes a COP reset to occur. Technical Data 173 Clock Functions 1 Bit 0 1 Bit $0017 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 174

... Clock Functions Technical Data 174 MC68HC912D60A — Rev. 3.1 Clock Functions Freescale Semiconductor ...

Page 175

... In order to make the HC12 D-family oscillator options more flexible, a Pierce oscillator configuration has been implemented on the 3L02H mask set. This implementation, described in section MC68HC912D60P Pierce Oscillator MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 MC68HC912D60A Oscillator Specification 176 MC68HC912D60C Colpitts Oscillator Specification . . . . . . . . 179 MC68HC912D60P Pierce Oscillator Specification . . . . . . . . . 194 12 ...

Page 176

... This section applies to the 1L02H mask set and all previous MC68HC912D60A versions. 12.3.1 MC68HC912D60A Oscillator Design Architecture The Colpitts oscillator architecture is shown in component configuration for this oscillator is the same as all previous MC68HC912D60A configurations. Technical Data 176 Figure MC68HC912D60A — Rev. 3.1 Oscillator 12-1. The Freescale Semiconductor ...

Page 177

... Poor layout of the application board can contribute to EMC susceptibility, noise generation, slow starting oscillators, and reaction to noise on the clock input buffer. In addition to published errata for the MC68HC912D60A, the following guidelines must be followed or failure in operation may occur. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor CFLT 2 RFLT RFLT CFLT ...

Page 178

... Observe best practice supply bypassing on all MCU power pins. The oscillator’s supply reference is VDD, not VDDPLL. Account for XTAL–VSS and EXTAL–XTAL parasitics in component values. Minimize XTAL and EXTAL routing lengths to reduce EMC issues. Oscillator MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 179

... The name for these devices is MC68HC912D60C. 12.4.1 MC68HC912D60C Oscillator Design Architecture The Colpitts oscillator architecture is shown in component configuration for this oscillator is the same as all previous MC68HC912D60A configurations. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60C Colpitts Oscillator Specification Figure Oscillator Oscillator 12-2. The Technical Data ...

Page 180

... RFLT CFLT EXTAL Resonator Hysteresis was added to the clock input buffer to reduce sensitivity to noise Internal parasitics were reduced from EXTAL to VSS to increase oscillator gain margin. Oscillator BUF - OTA + - ALC BIAS + EN GM RESD XTAL C X-EX C X-VSS MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 181

... The minimum amplitude of oscillation is expected excess of 750mV and the maximum hysteresis is expected to be less than 350mV, providing a factor of safety in excess of two. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60C Colpitts Oscillator Specification The bias current to the amplifier was optimized for less variation over process. ...

Page 182

... To reduce the process sensitivity of the gain, the material of the device that sets the bias current was changed to a material with tighter process and temperature control result, the transconductance and Ibias variances are more limited than in the previous design. Technical Data 182 MC68HC912D60A — Rev. 3.1 Oscillator Freescale Semiconductor ...

Page 183

... ALC and the OTA) and oscillator transconductance amplifier (marked GM in the figure above parallel path. In this configuration, the only capacitance causing a phase shift on the input to the transconductance device is due to the transconductance device itself. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60C Colpitts Oscillator Specification Oscillator Oscillator Technical Data ...

Page 184

... NRM vs. capacitance curve is very steep, indicating severe sensitivity to small variations). If the NRM optimization happened to be performed on a best-case sample set, there could be unexpected sensitivity at worst- case. Technical Data 184 Negative Resistance Margin vs. Capacitance Capacitance Oscillator 1000 WCS TYP 100 TYP BCS MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 185

... ESR. However, since typical NRM is likely to be higher and most measurement techniques do not account for ALC effects, actual NRM measurements are likely to be much higher. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60C Colpitts Oscillator Specification Oscillator Oscillator Technical Data ...

Page 186

... XTAL–VSS capacitor value — The value of the component plus external (board) parasitic in excess of 1.0pF between XTAL and VSS. Maximum Shunt Capacitance — The maximum value of the resonator’s shunt capacitance (C0) plus the external (board) parasitics in excess of 1pF from EXTAL to VSS. Oscillator MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 187

... Choose the set of component values corresponding to the correct 2. Determine the range of components for which the Maximum ESR MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60C Colpitts Oscillator Specification VDDPLL Setting — The Voltage applied to the VDDPLL pin (Logic 1 means VDDPLL is tied to the same potential as VDD). ...

Page 188

... Ceramic resonators with integrated components should not be used, as they are designed for Pierce-configured oscillators. Series cut resonators should not be used. Use parallel cut instead. The Load Capacitance should be 12pF or higher, preferably greater than 15pF. Oscillator = 0.82*C ). EXTAL–XTAL MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 189

... Shunt 5 Capacitance (pF) 7 (VDDPLL=VDD Shunt 5 Capacitance (pF) 7 (VDDPLL= (pF) EXTAL-XTAL MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60C Colpitts Oscillator Specification Capacitance, and VDDPLL setting 2080 2620 2700 1870 1890 2340 2010 1370 1730 2100 1550 1050 1520 1600 1100 740 82pF 68pF ...

Page 190

... Not allowed 12.4.3.1 How to Use This Information Oscillator 105 115 22pF 18pF 13pF 10pF 22pF 18pF 13pF 10pF 22pF 18pF 13pF 10pF for important information regarding shunt ca- MC68HC912D60A — Rev. 3.1 Freescale Semiconductor 90 70 104 ...

Page 191

... The value of the DC-blocking capacitor should be between 0.1 and 10nF, with a preferred value of 1nF. This capacitor must be connected as shown in specifications and guidelines continue to apply. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60C Colpitts Oscillator Specification Figure 12-3. Figure 12-3. If connected thus, all other oscillator ...

Page 192

... Oscillator Figure 12-3. MC68HC912D60C Crystal with DC Blocking Capacitor Technical Data 192 - OTA CFLT + 2 RFLT - ALC + RFLT CFLT RESD EXTAL Resonator 1nF DC-blocking capacitor C DC Oscillator BUF BIAS EN GM XTAL C X-EX C X-VSS MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 193

... An increase in the EXTAL–XTAL parasitic as a result of reducing EXTAL–VSS parasitic is acceptable provided component value is reduced by the appropriate value. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60C Colpitts Oscillator Specification Minimize Capacitance to VSS on EXTAL pin — The Colpitts oscillator architecture is sensitive to capacitance in parallel with the resonator (from EXTAL to VSS) ...

Page 194

... MC68HC912D60A configurations and the recommended components may be different. Please note carefully the connection of external capacitors and the resonator in this diagram. Technical Data 194 Minimize XTAL and EXTAL routing lengths to reduce EMC issues. Oscillator Figure 12-4. The MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 195

... There are the following primary differences between the previous Colpitts (‘A’) and new Pierce (‘P’) oscillator configurations: • • • MC68HC912D60A — Rev. 3.1 Freescale Semiconductor CFLT 2 RFLT EXTAL Figure 12-4. MC68HC912D60P Pierce Oscillator Architecture Oscillator architecture was changed from Colpitts to Pierce. ...

Page 196

... Amplitude Level Control (ALC) circuit for both architectures. The circuit responds slightly differently to the different DC offsets in the two architectures, resulting in slightly Oscillator MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...

Page 197

... MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60P Pierce Oscillator Specification lower amplitude for the Pierce. The amplitude will still be sufficient for robust operation across process, temperature, and voltage variance ...

Page 198

... ALC and the OTA) and oscillator transconductance amplifier (marked GM in the figure above parallel path. In this configuration, the only capacitance causing a phase shift on the input to the transconductance device is due to the transconductance device itself. Technical Data 198 MC68HC912D60A — Rev. 3.1 Oscillator Freescale Semiconductor ...

Page 199

... NRM vs. capacitance curve is very steep, indicating severe sensitivity to small variations). If the NRM optimization happened to be performed on a best-case sample set, there could be unexpected sensitivity at worst- case. MC68HC912D60A — Rev. 3.1 Freescale Semiconductor MC68HC912D60P Pierce Oscillator Specification Negative Resistance Margin vs. Capacitance 8 10 ...

Page 200

... ESR. However, since typical NRM is likely to be higher and most measurement techniques do not account for ALC effects, actual NRM measurements are likely to be much higher. Technical Data 200 MC68HC912D60A — Rev. 3.1 Oscillator Freescale Semiconductor ...

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