MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 309

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4.3 Transmit Structures
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
An overrun condition occurs when both the foreground and the
background receive message buffers are filled with correctly received
messages with accepted identifiers and another message is correctly
received from the bus with an accepted identifier. The latter message is
discarded and an error interrupt with overrun indication is generated if
enabled. The msCAN12 is still able to transmit messages with both
receive message buffers filled, but all incoming messages are
discarded.
The msCAN12 has a triple transmit buffer scheme in order to allow
multiple messages to be set up in advance and to achieve an optimized
real-time performance. The three buffers are arranged as shown in
Figure
All three buffers have a 13 byte data structure similar to the outline of the
receive buffers (see
additional transmit buffer priority register (TBPR) contains an 8-bit so
called local priority field (PRIO) (see
(TBPR)).
In order to transmit a message, the CPU12 has to identify an available
transmit buffer which is indicated by a set transmit buffer empty (TXE)
flag in the msCAN12 transmitter flag register (CTFLG) (see
Transmitter Flag Register
The CPU12 then stores the identifier, the control bits and the data
content into one of the transmit buffers. Finally, the buffer has to be
flagged as being ready for transmission by clearing the TXE flag.
The msCAN12 will then schedule the message for transmission and will
signal the successful transmission of the buffer by setting the TXE flag.
A transmit interrupt will be emitted
used to drive the application software to re-load the buffer.
1. The transmit interrupt is generated only if not masked. A polling scheme can be applied on
TXE also.
17-2.
MSCAN Controller
Programmer’s Model of Message
(CTFLG)).
(1)
Transmit Buffer Priority Registers
when TXE is set and this can be
Storage). An
MSCAN Controller
Message Storage
Technical Data
msCAN12
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