MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 280

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Multiple Serial Interface
15.5.4 Bidirectional Mode (MOMI or SISO)
15.5.5 Register Descriptions
SP0CR1 — SPI Control Register 1
Technical Data
280
RESET:
When SPE=1
Bidirectional
SPC0=0
SPC0=1
Normal
Mode
Mode
SPIE
Bit 7
0
SWOM enables open drain output. PS4 becomes GPIO.
Figure 15-6. Normal Mode and Bidirectional Mode
Serial Out
Serial Out
Serial In
Serial In
SPI
SPI
SPE
SWOM enables open drain output.
6
0
In bidirectional mode, the SPI uses only one serial data pin for external
device interface. The MSTR bit decides which pin to be used. The MOSI
pin becomes serial data I/O (MOMI) pin for the master mode, and the
MISO pin becomes serial data I/O (SISO) pin for the slave mode. The
direction of each serial I/O pin depends on the corresponding DDRS bit.
Control and data registers for the SPI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. For more information refer to
and Resource
Read or write anytime.
Master Mode
MSTR=1
DDS5
DDS5
SWOM
5
0
Multiple Serial Interface
Mapping.
MSTR
MOMI
4
0
PS4
MO
MI
CPOL
3
0
SWOM enables open drain output. PS5 becomes GPIO.
Serial Out
Serial Out
Serial In
Serial In
SPI
SPI
CPHA
SWOM enables open drain output.
2
1
Slave Mode
DDS4
DDS4
MSTR=0
SSOE
MC68HC912D60A — Rev. 3.1
1
0
Freescale Semiconductor
Operating Modes
LSBF
Bit 0
SISO
PS5
0
SO
SI
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