MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 452

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Glossary
memory location — Each M68HC12 memory location holds one byte of data and has a unique
memory map — A pictorial representation of all memory locations in a computer system.
MI-Bus — See "Freescale interconnect bus".
microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU,
modulo counter — A counter that can be programmed to count to any number from zero to its
most significant bit (MSB) — The leftmost digit of a binary number.
Freescale interconnect bus (MI-Bus) — The Freescale Interconnect Bus (MI Bus) is a serial
Freescale scalable CAN (msCAN) — The Scalable controller area network is a serial
msCAN — See "Scalable CAN".
MSI — See "multiple serial interface".
multiple serial interface — A module consisting of multiple independent serial I/O sub-systems,
multiplexer — A device that can select one of a number of inputs and pass the logic level of that
nibble — A set of four bits (half of a byte).
object code — The output from an assembler or compiler that is itself executable machine code,
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
Technical Data
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address. To store information in a memory location, the CPU places the address of the
location on the address bus, the data information on the data bus, and asserts the write
signal. To read information from a memory location, the CPU places the address of the
location on the address bus and asserts the read signal. In response to the read signal,
the selected memory location places its data onto the data bus.
memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.
maximum possible modulus.
communications protocol which supports distributed real-time control efficiently and with
a high degree of noise immunity.
communications protocol that efficiently supports distributed real-time control with a very
high level of data integrity.
e.g. two SCI and one SPI.
input on to the output.
or is suitable for processing to produce executable machine code.
connected to the power supply to provide the logic 1 output voltage.
Glossary
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor