MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 249

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCFLG — 16-Bit Modulus Down-Counter FLAG Register
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
RESET:
MCZF
BIT 7
0
6
0
0
MCEN — Modulus Down-Counter Enable
MCPR1, MCPR0 — Modulus Counter Prescaler select
Read: any time
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Interrupt Flag
When MCEN=0, the counter is preset to $FFFF. This will prevent an
early interrupt flag when the modulus down-counter is enabled.
These two bits specify the division rate of the modulus counter
prescaler.
The newly selected prescaler division rate will not be effective until a
load of the load register into the modulus counter count register
occurs.
The flag is set when the modulus down-counter reaches $0000.
Writing a1 to this bit clears the flag (if TFFCA=0). Writing zero has no
effect.
Any access to the MCCNT register will clear the MCZF flag in this
register when TFFCA bit in register TSCR($86) is set.
0 = Modulus counter disabled.
1 = Modulus counter is enabled.
0
5
0
Enhanced Capture Timer
MCPR1
0
4
0
0
0
1
1
POLF3
MCPR0
3
0
0
1
0
1
POLF2
2
0
Prescaler division
rate
16
1
4
8
POLF1
1
0
Enhanced Capture Timer
POLF0
BIT 0
0
Timer Registers
Technical Data
$00A7
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