MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 325

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.12 Programmer’s Model of Message Storage
17.12.1 Message Buffer Outline
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
The following section details the organisation of the receive and transmit
message buffers and the associated control registers. For reasons of
programmer interface simplification the receive and transmit message
buffers have the same outline. Each message buffer allocates 16 bytes
in the memory map containing a 13 byte data structure. An additional
transmit buffer priority register (TBPR) is defined for the transmit buffers.
Figure 17-11
transmit buffers for extended identifiers. The mapping of standard
identifiers into the IDR registers is shown in
13 byte data structure are undefined out of reset.
Figure 17-10. Message Buffer Organization
shows the common 13 byte data structure of receive and
Address
1. x is 4, 5, 6, or 7 depending on which buffer RxFG,
2. Not applicable for receive buffers
MSCAN Controller
Tx0, Tx1, or Tx2 respectively.
01xC
01xD
01xA
01xB
01xE
01xF
01x0
01x1
01x2
01x3
01x4
01x5
01x6
01x7
01x8
01x9
(1)
Transmit buffer priority register
Data segment register 0
Data segment register 1
Data segment register 2
Data segment register 3
Data segment register 4
Data segment register 5
Data segment register 6
Data segment register 7
Data length register
Identifier register 0
Identifier register 1
Identifier register 2
Identifier register 3
Register name
Programmer’s Model of Message Storage
Unused
Unused
Figure
17-12. All bits of the
(2)
MSCAN Controller
Technical Data
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