MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 217

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PWCNTx — PWM Channel Counters
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
PWCNT0
PWCNT1
PWCNT2
PWCNT3
RESET:
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
Read and write anytime. A write will cause the PWM counter to reset to
$00.
In special mode, if DISCR = 1, a write does not reset the PWM counter.
The PWM counters are not reset when PWM channels are disabled. The
counters must be reset prior to a new enable.
Each counter may be read any time without affecting the count or the
operation of the corresponding PWM channel. Writes to a counter cause
the counter to be reset to $00 and force an immediate load of both duty
and period registers with new values. To avoid a truncated PWM period,
write to a counter while the counter is disabled. In left-aligned output
mode, resetting the counter and starting the waveform output is
controlled by a match between the period register and the value in the
counter. In center-aligned output mode the counters operate as up/down
counters, where a match in period changes the counter direction. The
duty register changes the state of the output during the period to
determine the duty.
When a channel is enabled, the associated PWM counter starts at the
count in the PWCNTx register using the clock selected for that channel.
In special mode, when DISCP = 1 and configured for left-aligned output,
a match of period does not reset the associated PWM counter.
6
6
6
6
6
0
5
5
5
5
5
0
Pulse Width Modulator
4
4
4
4
4
0
3
3
3
3
3
0
2
2
2
2
2
0
1
1
1
1
1
0
PWM Register Description
Pulse Width Modulator
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
Technical Data
$004A
$004B
$0048
$0049
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