MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 77

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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5.5 Internal Resource Mapping
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
EME — Emulate Port E
The internal register block, RAM, and EEPROM have default locations
within the 64K byte standard address space but may be reassigned to
other locations during program execution by setting bits in mapping
registers INITRG, INITRM, and INITEE. During normal operating modes
these registers can be written once. It is advisable to explicitly establish
these resource locations during the initialization phase of program
execution, even if default values are chosen, in order to protect the
registers from inadvertent modification later.
Writes to the mapping registers go into effect between the cycle that
follows the write and the cycle after that. To assure that there are no
unintended operations, a write to one of these registers should be
followed with a NOP instruction.
If conflicts occur when mapping resources, the register block will take
precedence over the other resources; RAM or EEPROM addresses
occupied by the register block will not be available for storage. When
active, BDM ROM takes precedence over other resources, although a
conflict between BDM ROM and register space is not possible. The
following table shows resource mapping precedence.
In expanded modes, all address space not used by internal resources is
by default external memory.
The MC68HC912D60A contains 60K bytes of Flash EEPROM
nonvolatile memory which can be used to store program code or static
In single-chip mode PORTE and DDRE are always in the map
regardless of the state of this bit.
0 = PORTE and DDRE are in the memory map.
1 = If in an expanded mode, PORTE and DDRE are removed from the
internal memory map. Removing the registers from the map allows
the user to emulate the function of these registers externally.
Normal modes: write once; special modes: write anytime EXCEPT
the first time. Read anytime.
Operating Modes and Resource Mapping
Operating Modes and Resource Mapping
Internal Resource Mapping
Technical Data
77

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