MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 361

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
DJM — Result Register Data Justification Mode
exited, the ATD module powers up and continues operation. The
module is not reset; the register file is not reinitialized; the conversion
sequence is not restarted.
When the module comes out of wait, it is recommended that a
stabilization delay ( t
started.
For 10-bit resolution, left justified mode maps a result register into
data bus bits 6 through 15; bit 15 is the MSB. In right justified mode,
the result registers maps onto data bus bits 0 through 9; bit 9 is the
MSB.
For 8-bit resolution, left justified mode maps a result into the high byte
(bits 8 though 15; bit 15 is the MSB). Right justified maps a result into
the low byte (bits 0 through 7; bit 7 is the MSB).
Table 18-1
they are set up using the control bits.
Table 18-2
range between 0 and 5.1 Volts.
0 = Left justified mode
1 = Right justified mode
RES10
0
0
1
1
Analog-to-Digital Converter
Table 18-1. Result Data Formats Available
summarizes the result data formats available and how
illustrates left justified output codes for an input signal
DJM
0
1
0
1
SR
) is allowed before new conversions are
Description and Bus Bit Mapping
10-bit/left justified - bits 6-15
10-bit/right justified - bits 0-9
8-bit/left justified - bits 8-15
8-bit/right justified - bits 0-7
Result Data Formats
Analog-to-Digital Converter
Technical Data
ATD Registers
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