EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 1015

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–18. MegaWizard Plug-In Manager Options (SONET/SDH Screen) (Part 3 of 3)
February 2011 Altera Corporation
Create a rx_invpolarity port to
enable word aligner polarity
inversion.
Create a tx_invpolarity port to
allow Transmitter polarity
inversion.
Flip receiver output data bits.
Flip transmitter input data bits.
ALTGX Setting
This optional port allows you to dynamically reverse
the polarity of every bit of the received data at the
input of the word aligner. Use this option when the
positive and negative signals of the differential input
to the receiver (rx_datain) are erroneously
swapped on the board.
This optional port allows you to dynamically reverse
the polarity of every bit of the data word fed to the
serializer in the transmitter data path. Use this
option when the positive and negative signals of the
differential output from the transmitter
(tx_dataout) are erroneously swapped on the
board.
This option reverses the bit order of the parallel
receiver data at a byte level at the output of the
receiver phase compensation FIFO to support
MSB-to-LSB transmission in SONET/SDH mode.
For example, if the 16-bit parallel receiver data at the
output of the receiver phase compensation FIFO is
'10111100 10101101' (16'hBCAD), enabling this
option reverses the data on the rx_dataout port to
'00111101 10110101' (16'h3DB5).
This option reverses the bit order of the parallel
transmitter data at a byte level at the input of the
transmitter phase compensation FIFO to support
MSB-to-LSB transmission protocols in SONET/SDH
mode.
For example, if the 16-bit parallel transmitter data at
the tx_datain port is '10111100 10101101'
(16'hBCAD), enabling this option reverses the input
data to the transmitter phase compensation FIFO to
'00111101 10110101' (16'h3DB5).
Description
“Receiver Polarity Inversion”
section in the
Architecture in Stratix IV
Devices
“Transmitter Polarity Inversion”
section in the
Architecture in Stratix IV
Devices
“SONET/SDH Mode” (OC-12,
OC-48, and OC-96) section in
the
Stratix IV Devices
“SONET/SDH Mode” (OC-12,
OC-48, and OC-96) section in
the
Stratix IV Devices
Stratix IV Device Handbook Volume 3
Transceiver Architecture in
Transceiver Architecture in
chapter.
chapter.
Reference
Transceiver
Transceiver
chapter.
chapter.
1–57