EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 378

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

10–44
Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 3 of 4)
Stratix IV Device Handbook Volume 1
nSTATUS
(continued)
CONF_DONE
nCE
nCEO
ASDO
Pin Name
User Mode
N/A
N/A
N/A
N/A
—
Configuration
Scheme
AS
—
All
All
All
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Bidirectional
open-drain
Pin Type
Output
Output
Input
—
If V
■
■
Status output. The target device drives the CONF_DONE pin
low before and during configuration. After all the
configuration data is received without error and the
initialization cycle starts, the target device releases
CONF_DONE.
Status input. After all the data is received and CONF_DONE
goes high, the target device initializes and enters user
mode. The CONF_DONE pin must have an external 10-kΩ
pull-up resistor for the device to initialize.
Driving CONF_DONE low after configuration and initialization
does not affect the configured device.
Active-low chip enable. The nCE pin activates the device
with a low signal to allow configuration. The nCE pin must
be held low during configuration, initialization, and user
mode. In single device configuration, it must be tied low. In
multi-device configuration, nCE of the first device is tied
low, while its nCEO pin is connected to nCE of the next
device in the chain.
The nCE pin must also be held low for successful JTAG
programming of the device.
Output that drives low when device configuration is
complete. In single device configuration, this pin is left
floating. In multi-device configuration, this pin feeds the
next device’s nCE pin. The nCEO of the last device in the
chain is left floating.
The nCEO pin is powered by V
Control signal from the Stratix IV device to the serial
configuration device in AS mode used to read out
configuration data.
In AS mode, ASDO has an internal pull-up resistor that is
always active.
V
to function properly and nSTATUS is driven low. When
V
after POR expires.
V
buffer to function properly. In this situation, nSTATUS
might appear logic high, triggering a configuration
attempt that would fail because POR did not yet trip.
When V
because POR did not yet trip. When POR trips after
V
high. At that point, reconfiguration is triggered and the
device is configured.
CCPGM
CCPGM
CCPGM
CCPGM
CCPGM
is not fully powered up, the following could occur:
is ramped up, POR trips and nSTATUS is released
is powered high enough for the nSTATUS buffer
is not powered high enough for the nSTATUS
is powered up, nSTATUS is released and pulled
CCPD
is powered up, nSTATUS is pulled low
Description
CCPGM
April 2011 Altera Corporation
.
Device Configuration Pins