EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 380

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

10–46
Table 10–11. Optional Configuration Pins
Stratix IV Device Handbook Volume 1
CLKUSR
INIT_DONE
DEV_OE
DEV_CLRn
Pin Name
N/A if option is on.
I/O if option is off.
N/A if option is on.
I/O if option is off.
N/A if option is on.
I/O if option is off.
N/A if option is on.
I/O if option is off.
User Mode
Table 10–11
are not enabled in the Quartus II software, they are available as general-purpose user
I/O pins. Therefore, during configuration, these pins function as user I/O pins and
are tri-stated with weak pull-up resistors.
lists the optional configuration pins. If these optional configuration pins
open-drain
Pin Type
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Output
Input
Input
Input
Optional user-supplied clock input synchronizes the initialization of
one or more devices. Enable this pin by turning on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II
software.
Use as a status pin to indicate when the device has initialized and is
in user mode. When nCONFIG is low and during the beginning of
configuration, the INIT_DONE pin is tri-stated and pulled high due to
an external 10-kΩ pull-up resistor. After the option bit to enable
INIT_DONE is programmed into the device (during the first frame of
configuration data), the INIT_DONE pin goes low. When initialization
is complete, the INIT_DONE pin is released and pulled high and the
device enters user mode. Thus, the monitoring circuitry must be able
to detect a low-to-high transition. Enable this pin by turning on the
Enable INIT_DONE output option in the Quartus II software.
Optional pin that allows you to override all tri-states on the device.
When this pin is driven low, all I/O pins are tri-stated. When this pin
is driven high, all I/O pins behave as programmed. Enable this pin by
turning on the Enable device-wide output enable (DEV_OE) option
in the Quartus II software.
Optional pin that allows you to override all clears on all device
registers. When this pin is driven low, all registers are cleared. When
this pin is driven high, all registers behave as programmed. Enable
this pin by turning on the Enable device-wide reset (DEV_CLRn)
option in the Quartus II software.
Description
April 2011 Altera Corporation
Device Configuration Pins