EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 130

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

5–14
Stratix IV Device Handbook Volume 1
Clock Control Block
Table 5–6. Stratix IV RCLK Outputs From the PLL Clock Outputs
Every GCLK and RCLK network has its own clock control block. The control block
provides the following features:
■
■
■
Figure 5–11
You can select the clock source for the GCLK select block either statically or
dynamically. You can statically select the clock source using a setting in the Quartus II
software or you can dynamically select the clock source using internal logic to drive
the multiplexer-select inputs. When selecting the clock source dynamically, you can
select either PLL outputs (such as C0 or C1) or a combination of clock pins or PLL
outputs.
Figure 5–11. Stratix IV GCLK Control Block
Notes to
(1) When the device is operating in user mode, you can dynamically control the clock select signals through internal
(2) When the device is operation in user mode, you can only set the clock select signals through a configuration file
RCLK[64..69]
RCLK[70..75]
RCLK[76..81]
RCLK[82..87]
Note to
(1) All PLL counter outputs can drive the RCLK networks.
Clock Resource
Clock source selection (dynamic selection for GCLKs)
Global clock multiplexing
Clock power down (static or dynamic clock enable or disable)
logic.
(SRAM object file [.sof] or programmer object file [.pof]) and cannot be dynamically controlled.
Figure
Table
5–6:
and
5–11:
Figure 5–12
v
L1
—
—
—
CLKSELECT[1..0]
PLL Counter
This multiplexer
supports user-controllable
dynamic switching
L2
—
—
—
—
Outputs
(1)
show the GCLK and RCLK select blocks, respectively.
—
—
—
—
L3
2
2
v
L4
—
—
—
CLKp
Pins
B1
—
—
—
—
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
2
PLL Number
B2
—
—
—
—
Enable/
Disable
GCLK
CLKn
Pin
v
R1
—
—
—
Static Clock
Select (2)
(Note 1)
Internal
Internal
Logic
Logic
Clock Networks in Stratix IV Devices
R2
—
—
—
—
February 2011 Altera Corporation
(Part 2 of 2)
R3
—
—
—
—
v
R4
—
—
—
T1
—
—
—
—
T2
—
—
—
—