EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 216

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

6–44
Stratix IV Device Handbook Volume 1
Differential LVPECL
In Stratix IV devices, the LVPECL I/O standard is supported on input clock pins on
column and row I/O banks. LVPECL output operation is not supported in Stratix IV
devices. LVDS input buffers are used to support LVPECL input operation. AC
coupling is required when the LVPECL common-mode voltage of the output buffer is
higher than the LVPECL input common-mode voltage.
AC-coupled termination scheme. The 50-
external to the device.
Figure 6–32. LVPECL AC-Coupled Termination
Note to
(1) The LVPECL AC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
DC-coupled LVPECL is supported if the LVPECL output common mode voltage is
within the Stratix IV LVPECL input buffer specification
Figure 6–33. LVPECL DC-Coupled Termination
Note to
(1) The LVPECL DC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
Figure
Figure
LVPECL Output Buffer
LVPECL Output Buffer
6–32:
6–33:
Altera FPGA
Altera FPGA
0.1 μF
0.1 μF
Z
Z
Z
Z
O
O
O
O
= 50 Ω
= 50 Ω
= 50 Ω
= 50 Ω
Ω
(Note 1)
(Note 1)
resistors used at the receiver end are
V
ICM
100 Ω
Chapter 6: I/O Features in Stratix IV Devices
Figure 6–32
(Figure
50 Ω
50 Ω
Termination Schemes for I/O Standards
Stratix IV LVPECL
February 2011 Altera Corporation
Stratix IV LVPECL
Input Buffer
6–33).
Input Buffer
shows the