EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 1040

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–22
Figure 2–5. FC4G Instance Settings (PLL/Ports Screen)
Stratix IV Device Handbook Volume 3
f
■
For more information about receiver CDR and lock modes, refer to the “Receiver
Channel Datapath” section of
PLL/Ports screen—Check the Train Receiver CDR from PLL inclk option, as
shown in
used for the CMU PLL is provided as a training clock to the receiver CDR.
■
■
■
Check the pll_powerdown signal. This signal allows you to power down the
CMU PLL. Use this signal as part of your reset sequence.
Check the pll_locked signal. This signal indicates whether the CMU PLL is
locked to the input reference clock. The user logic waits until the pll_locked
signal goes high before transmitting data.
Check the rx_freqlocked signal. This signal indicates whether the receiver
CDR is locked to data. When the receiver CDR is configured in automatic lock
mode, assert the rx_digitalreset signal if the rx_freqlocked signal goes low
to keep the receiver PCS under reset. Altera recommends specific transceiver
reset sequences to ensure proper device operation.
Figure
2–5. When you select this option, the same input reference clock
Transceiver Architecture in Stratix IV Devices
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
February 2011 Altera Corporation
chapter.