EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 468

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–24
Figure 1–19. Control Word and Data Word Transmission
Stratix IV Device Handbook Volume 2: Transceivers
tx_datain[7:0]
tx_ctrlenable
code group
clock
Figure 1–18
Figure 1–18. 8B/10B Conversion Format
The ALTGX MegaWizard Plug-In Manager provides the tx_ctrlenable port to
indicate whether the 8-bit data at the tx_datain port should be encoded as a control
word (Kx.y). When tx_ctrlenable is low, the 8B/10B encoder block encodes the byte
at the tx_datain port (the user-input port) as data (Dx.y). When tx_ctrlenable is
high, the 8B/10B encoder encodes the input data as a Kx.y code group. The waveform
in
the tx_datain bytes are encoded as a data word (Dx.y).
The IEEE 802.3 8B/10B encoder specification identifies only a set of 8-bit characters
for which tx_ctrlenable should be asserted. If you assert tx_ctrlenable for any
other set of bytes, the 8B/10B encoder might encode the output 10-bit code as an
invalid code (it does not map to a valid Dx.y or Kx.y code), or unintended valid Dx.y
code, depending on the value entered. It is possible for a downstream 8B/10B decoder
to decode an invalid control word into a valid Dx.y code without asserting code error
flags.
Figure 1–19
Control Code Encoding
D3.4
83
shows the conversion format. The LSB is transmitted first.
shows the second 0 × BC encoded as a control word (K28.5). The rest of
D24.3
78
H G F E D C B A
7
MSB
j
9
6
BC
D28.5
h
8
5
g
7
4
8B/10B Conversion
K28.5
f
6
BC
3
i
5
2
e d c b a
4
1
D15.0
0F
Chapter 1: Transceiver Architecture in Stratix IV Devices
3
0
2
1
D0.0
control_code
00
LSB
0
D31.5
BF
February 2011 Altera Corporation
Transceiver Block Architecture
D28.1
3C