EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 126

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

5–10
Figure 5–10. Stratix IV Dual-Regional Clock Region
Stratix IV Device Handbook Volume 1
Clock Network Sources
1
To form a RCLK region, a source drives a single quadrant of the device. This clock
region provides the lowest skew within a quadrant and is a good option if all the
destinations are within a single device quadrant.
To form a dual-regional clock region, a single source (a clock pin or PLL output)
generates a dual-regional clock by driving two RCLK networks (one from each
quadrant). This technique allows destinations across two device quadrants to use the
same low-skew clock. The routing of this signal on an entire side has approximately
the same delay as a RCLK region. Internal logic can also drive a dual-regional clock
network. Corner PLL outputs only span one quadrant, they cannot generate a
dual-regional clock network.
In Stratix IV devices, clock input pins, PLL outputs, and internal logic can drive the
GCLK and RCLK networks. For connectivity between dedicated pins CLK[0..15] and
the GCLK and RCLK networks, refer to
Dedicated Clock Input Pins
Clock pins can be either differential clocks or single-ended clocks. Stratix IV devices
support 16 differential clock inputs or 32 single-ended clock inputs. You can also use
dedicated clock input pins CLK[15..0] for high fan-out control signals such as
asynchronous clears, presets, and clock enables for protocol signals such as TRDY and
IRDY for PCIe through the GCLK or RCLK networks.
LABs
You can drive each GCLK and RCLK network using LAB-routing to enable internal
logic to drive a high fan-out, low-skew signal.
Stratix IV PLLs cannot be driven by internally generated GCLKs or RCLKs. The input
clock to the PLL has to come from dedicated clock input pins or pin/PLL-fed GCLKs
or RCLKs.
Figure 5–10
Table 5–2
shows the dual-regional clock region.
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
and
Clock pins or PLL outputs
can drive half of the device to
create side-wide clocking
regions for improved
interface timing.
Table 5–3 on page
Clock Networks in Stratix IV Devices
February 2011 Altera Corporation
5–11.