EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 792

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

3–38
Stratix IV Device Handbook Volume 2: Transceivers
You can place these two instances in two transceiver blocks, as shown in
Figure 3–20. Combining Basic (PMA Direct) ×N Configuration with Non-Basic (PMA Direct)
Configuration Using CMU PLL in Two Transceiver Blocks For Example 9
Note to
(1) The red lines represent the ×N top clock line, the blue lines represent the ×4 clock line, and the black line represents
the ×N bottom clock line.
Figure
3–20:
CMU0
PLL
CMU0 Channel
Inst0:Channel 0
Inst0:Channel 1
Inst0:Channel 2
Inst0:Channel 3
Inst0:Channel 4
Inst0:Channel 5
Inst0:Channel 6
Inst0:Channel 7
Inst0:Channel 8
Inst1:Channel 0
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
Inst0:Channel 1
Inst0:Channel 1
(1.25 Gbps)
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
CMU PLL
GXBR0
GXBR1
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
Central
Divider
Clock
Combining Transceiver Channels in Basic (PMA Direct) Configurations
x1 Clock Line
x4 Clock Line (1)
xN Top Clock Line (1)
February 2011 Altera Corporation
Figure
3–20.